I’ve used Cadstar for schematic capture and PCB layout for upwards of 15 years and have recently moved on to Eagle for reasons that are unimportant. The transition hasn’t been too bad. I went from downloading 5.11.0 3 days ago to what is an essentially completed layout today of what is a relatively simple board but have some questions that arose along the way.
During post-processing I noticed two things:
a) The information generated by the excellon.cam job in the .drd file is completely wrong. When viewed with all the gerbers (which seem okay) in Viewmate, the drill holes are all over the place. The offset is set to 0 and I used the excellon.cam file “as is.” Any thoughts?
b) In the solder resist gerbers (.stc and .sts) the vias are unmasked. I’d prefer they were masked. When I look a the layers only tStop or bStop is selected which means vias are present in these layers in the PCB layout. Can the via holes be easily removed from the tStop/bStop layers?
Is there some sort of “on line DRC” feature? I notice when I’m routing that I’m allowed to run one trace next to (in violation of spacings) or even on-top-of another or I can move vias in the same way (i.e. so they violate DRC with other elements or with each other). In Cadstar’s Route Editor it was possible to prevent this with DRC checks on the fly: Routes would not be allowed to be run in violation of rules and similarly, when moving vias or traces they could not move into violation. Does Eagle have anything similar?
When I open my board (.brd) file, the areas in which I previously poured copper have reverted to their “dashed-line” polygons. If I hit “ratsnest” the copper re-fills. Is this necessary? Why does it do this?
a) Not too sure about what’s going on there, would you mind sending me a copy of the board, and the files it outputs?
b) Go into the DRC menu, go to the “Masks” tab, and set “Limit” to the size of your (biggest) vias. I think by default they’ll all be masked after that.
Not that I’ve ever heard of, but it would be nice.
Basically, that’s just how it is I guess. I can’t say I really have a good answer. I actually prefer it to be unfilled while I’m editing the board because it’s a lot easier to see and otherwise I have to use the ratsnest command every time something moves.
I changed the eagle.def file [excellon] section to ResX and ResY of 1000 but still had the problem. I then checked Viewmate’s options before importing and did as donblake suggested (“Left of decimal: 2, Right of decimal: 3 and select Omit leading zeros”) and imported and this time it worked fine:
b) Go into the DRC menu, go to the “Masks” tab, and set “Limit” to the size of your (biggest) vias. I think by default they’ll all be masked after that.
Perfect. Worked great. Thank you.
Not that I’ve ever heard of, but it would be nice.
It’s not hard to do a DRC of course but the Cadstar method is pretty slick.
Basically, that’s just how it is I guess. I can’t say I really have a good answer. I actually prefer it to be unfilled while I’m editing the board because it’s a lot easier to see and otherwise I have to use the ratsnest command every time something moves.
Yes, this is true. It’ll no doubt take a while for me to get used to Eagle’s idiosyncrasies
Eagle’s “Follow-me” router is about as close as you’ll get to on-the-fly DRC. It’s extremely slow on a crowded board, so I’d rather freehand, run DRC, and make corrections.
