Enable SDRAM with AT91RM9200???

Development Boards MicroMod
1

Hello Guys,

I´m trying to flash an SDRAM with 8MB “MT48LC4M16A2” with AT91RM9200. Here is my config file:

telnet_port 4444
gdb_port 3333
interface ft2232
ft2232_device_desc "Amontec JTAGkey A"
ft2232_layout jtagkey
ft2232_vid_pid 0x0403 0xcff8
jtag_speed 2
reset_config trst_and_srst
jtag_device 4 0x1 0xf 0xe
jtag_nsrst_delay 250
jtag_ntrst_delay 250
daemon_startup reset 
target arm920t little run_and_init 0 arm920t
run_and_halt_time 0 30
target_script 0 reset c:\Programas\amontec\sdk4arm\ocd\openocd\bin\temp.ocd
working_area 0 0x20000000 0x200000 nobackup
flash bank cfi 0x00000000 0x800000 4 1 0

and script to enable the SDRAM:

mww 0xffffff00 0x00000001   # cancel reset remapping
mww 0xfffffc20 0x0000ff01   # PMC_MOR: Enable main oscillator, OSCOUNT = 0xff
# Init flash
mww 0xffffff10 0x00000000   # MC_PUIA[0]
mww 0xffffff50 0x00000000   # MC_PUP
mww 0xffffff54 0x00000000   # MC_PUER: Memory controller protection unit disable
mww 0xffffff64 0x00000000   # EBI_CFGR
mww 0xffffff70 0x00003284   # SMC_CSR[0]: 16bit, 2 TDF, 4 WS
mww 0xffffff78 0x00003284   # SMC_CSR[2]: 16bit, 2 TDF, 4 WS
mww 0xffffff8c 0x00004182   # SMC_CSR[7]:  8bit, 1 TDF, 2 WS
# Init clocks
mww 0xfffffc28 0x2026be04   # PLLAR: 179.712000 MHz for PCK
sleep 10
mww 0xfffffc2c 0x10483e0e   # PLLBR: 48.054857 MHz (divider by 2 for USB)
sleep 10
mww 0xfffffc30 0x00000202   # MCKR : PCK/3 = MCK Master Clock = 59.904000MHz from PLLA
sleep 10
# Init SDRAM
mww 0xfffff870 0xffff0000   # PIOC_ASR: Configure PIOC as peripheral (D16/D31)
mww 0xfffff874 0x00000000   # PIOC_BSR:
mww 0xfffff804 0xffff0000   # PIOC_PDR:
mww 0xffffff60 0x00000002   # EBI_CSA : CS1=SDRAM
mww 0xffffff64 0x00000000   # EBI_CFGR:
mww 0xffffff98 0x21914155   # SDRC_CR :
mww 0xffffff90 0x00000002   # SDRC_MR : Precharge All
mww 0x20000000 0x00000000   # access SDRAM
mww 0xffffff90 0x00000004   # SDRC_MR : Refresh
mww 0x20000000 0x00000000   # access SDRAM
mww 0x20000000 0x00000000   # access SDRAM
mww 0x20000000 0x00000000   # access SDRAM
mww 0x20000000 0x00000000   # access SDRAM
mww 0x20000000 0x00000000   # access SDRAM
mww 0x20000000 0x00000000   # access SDRAM
mww 0x20000000 0x00000000   # access SDRAM
mww 0x20000000 0x00000000   # access SDRAM
mww 0xffffff90 0x00000003   # SDRC_MR : Load Mode Register
mww 0x20000080 0x00000000   # access SDRAM
mww 0xffffff94 0x000002e0   # SDRC_TR : Write refresh rate
mww 0x20000000 0x00000000   # access SDRAM
mww 0xffffff90 0x00000000   # SDRC_MR : Normal Mode
mww 0x20000000 0x00000000   # access SDRAM

when i:

flash probe 0

Info:    configuration.c:50 configuration_output_handler(): probing failed for flash bank '#0' at 0x00000000

Can anyone help me?

Thanks in advance,

Filipe Moutinho

2

Lectularius:
Hello Guys,

I´m trying to flash an SDRAM with 8MB “MT48LC4M16A2” with AT91RM9200. Here is my config file:

telnet_port 4444

gdb_port 3333
interface ft2232
ft2232_device_desc “Amontec JTAGkey A”
ft2232_layout jtagkey
ft2232_vid_pid 0x0403 0xcff8
jtag_speed 2
reset_config trst_and_srst
jtag_device 4 0x1 0xf 0xe
jtag_nsrst_delay 250
jtag_ntrst_delay 250
daemon_startup reset
target arm920t little run_and_init 0 arm920t
run_and_halt_time 0 30
target_script 0 reset c:\Programas\amontec\sdk4arm\ocd\openocd\bin\temp.ocd
working_area 0 0x20000000 0x200000 nobackup
flash bank cfi 0x00000000 0x800000 4 1 0




and script to enable the SDRAM:

mww 0xffffff00 0x00000001 # cancel reset remapping
mww 0xfffffc20 0x0000ff01 # PMC_MOR: Enable main oscillator, OSCOUNT = 0xff

Init flash

mww 0xffffff10 0x00000000 # MC_PUIA[0]
mww 0xffffff50 0x00000000 # MC_PUP
mww 0xffffff54 0x00000000 # MC_PUER: Memory controller protection unit disable
mww 0xffffff64 0x00000000 # EBI_CFGR
mww 0xffffff70 0x00003284 # SMC_CSR[0]: 16bit, 2 TDF, 4 WS
mww 0xffffff78 0x00003284 # SMC_CSR[2]: 16bit, 2 TDF, 4 WS
mww 0xffffff8c 0x00004182 # SMC_CSR[7]: 8bit, 1 TDF, 2 WS

Init clocks

mww 0xfffffc28 0x2026be04 # PLLAR: 179.712000 MHz for PCK
sleep 10
mww 0xfffffc2c 0x10483e0e # PLLBR: 48.054857 MHz (divider by 2 for USB)
sleep 10
mww 0xfffffc30 0x00000202 # MCKR : PCK/3 = MCK Master Clock = 59.904000MHz from PLLA
sleep 10

Init SDRAM

mww 0xfffff870 0xffff0000 # PIOC_ASR: Configure PIOC as peripheral (D16/D31)
mww 0xfffff874 0x00000000 # PIOC_BSR:
mww 0xfffff804 0xffff0000 # PIOC_PDR:
mww 0xffffff60 0x00000002 # EBI_CSA : CS1=SDRAM
mww 0xffffff64 0x00000000 # EBI_CFGR:
mww 0xffffff98 0x21914155 # SDRC_CR :
mww 0xffffff90 0x00000002 # SDRC_MR : Precharge All
mww 0x20000000 0x00000000 # access SDRAM
mww 0xffffff90 0x00000004 # SDRC_MR : Refresh
mww 0x20000000 0x00000000 # access SDRAM
mww 0x20000000 0x00000000 # access SDRAM
mww 0x20000000 0x00000000 # access SDRAM
mww 0x20000000 0x00000000 # access SDRAM
mww 0x20000000 0x00000000 # access SDRAM
mww 0x20000000 0x00000000 # access SDRAM
mww 0x20000000 0x00000000 # access SDRAM
mww 0x20000000 0x00000000 # access SDRAM
mww 0xffffff90 0x00000003 # SDRC_MR : Load Mode Register
mww 0x20000080 0x00000000 # access SDRAM
mww 0xffffff94 0x000002e0 # SDRC_TR : Write refresh rate
mww 0x20000000 0x00000000 # access SDRAM
mww 0xffffff90 0x00000000 # SDRC_MR : Normal Mode
mww 0x20000000 0x00000000 # access SDRAM




when i:

flash probe 0

Info: configuration.c:50 configuration_output_handler(): probing failed for flash bank ‘#0’ at 0x00000000




Can anyone help me?



Thanks in advance,



Filipe Moutinho

Greetings,

Schematic?

Best regards

3

Hello Davemaster,

Thanks for the reply.

The code for enable the SDRAM is fine, and i can load a binary file to the SDRAM with ‘load_binary’ command.

The command ‘flash_cfi’ it´s only for flash memories type…I think so…?

Now i have another problem. In debug, i can´t stop in the breakpoint :? . I will open another topic, with that doubt.

Regards,

Filipe Moutinho