Thanks again for the pointers.
It seems that the board comes with the SDRAM disabled by default.
The following is one of the application notes for the configuration of the board, provided by Micrel.
It is long and I do not know if it will all be able to be posted here, but I am trying it.
I have read documentation and used the information provided in the files mentioned in the programming guide to set the base flash address etc, but I think I may well be mis-enterpreting the information, or as you have said other things may well need to be added, which I really have no idea as to what I need to provide OpenOCD with in order for it to be able to read/write/erase the flash. If it requires another script to be called then this also may be a major issue as I have not written any such script, just calling openocd with the file name of the configuration script.
I have used pdftotext to convert this document.
Application Note 125
BSP Flash Memory and SDRAM Support
KS8695P/PX
- Memory Layout
The KS8695P/PX supports two banks of flash memory and two banks of SDRAM. Each bank can be populated
with one, two, or four memory chips. When two or four chips populate a bank, the chips are said to be in parallel
and their memory cells are interleaved to form a contiguously addressable block of memory (see examples
below, where M + 0, M + 1, etc. denote byte addresses). Each bank is assigned a separate chip select (CS)
signal.
Examples of 8 bit chip(s) within a single bank:
· One 8 bit chip
Bank data width: 8 bit
Chip 0
M+0
M+1
|
CS
· Two 8 bit chips in parallel
Bank data width: 16 bit
Chip 0 Chip 1
M+0 M+1
M+2 M+3
|
CS
· Four 8 bit chips in parallel
Bank data width: 32 bit
Chip 0 Chip 1 Chip 2 Chip 3
M+0 M+1 M+2 M+3
M+4 M+5 M+6 M+7
|
CS
Examples of 16 bit chip(s) within a single bank:
· One 16 bit chip
Bank data width: 16 bit
Chip 0
M+0 M+1
M+2 M+3
|
CS
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· Two 16 bit chips in parallel
Bank data width: 32 bit
Chip 0 Chip 1
M+0 M+1 M+2 M+3
M+4 M+5 M+6 M+7
|
CS
Example of 32 bit chip within a single bank:
· One 32 bit chip
Bank data width: 32 bit
Chip 0
M+0 M+1 M+2 M+3
M+4 M+5 M+6 M+7
|
CS
- BSP
The KS8695P/PX Evaluation Kit provides you with an evaluation board populated with one bank of flash
memory and two banks of SDRAM. Also provided is board support program (BSP) software that is factory
configured to interface to these memories. When the evaluation board is booted, the BSP programs the
KS8695P/PX with the flash memory and SDRAM configuration. After this is completed, the KS8695P/PX can
read and write both flash memory and SDRAM.
If you elect to change the flash memory and/or SDRAM configuration, the BSP must be re-configured
accordingly. The BSP package provides a convenient way to do this. You simply select appropriate settings for
constant and macro definitions in the BSP source code files described below.
- File Soho/loader/include/KS8695.S
This file contains all of the constant definitions used by the bootloader and all of the hardware related constants
and macros.
Flash memory and SDRAM configuration information is defined in this file.
3.1 Flash Memory
The KS8695.S constant, listed below, defines the flash bank data width and chip access time. The evaluation
board uses an 8 bit data width and 72ns access time.
#define ROM_GENERAL_SETTING 0x00000001
Note: This value is written to register External I/O and ROM/SRAM/FLASH General Register (ERGCON Offset
0x4020) during BSP initialization.
3.1.1 Flash Memory Data Width
Modify bits 0-1 of the ROM_GENERAL_SETTING constant to use the following value denoting the appropriate
flash bank data width:
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Micrel Application Note 125
· 00b denotes the bank is disabled
· 01b denotes 8 bit data width
· 10b denotes 16 bit data width
· 11b denotes 32 bit data width
If you also put one or more flash chips into the second bank, then modify bits 2-3 to use an appropriate value
from the list above. On the demo board, the second bank of flash memory is disabled. If you use the second
bank of flash memory, you will need to write your own code to support this bank. The existing code that supports
the first bank of flash memory can be used as a template for writing your own code.
3.1.2 Flash Memory Access Time
Modify bits 28-29 of the ROM_GENERAL_SETTING constant to define the flash chip access time value
TMULT. The formula for selecting a TMULT value is:
(TMULT*8 + 9)*8 > flash chip access time
In the formula, flash chip access time is the access time of the flash chip you have selected.
Some examples:
· If your flash chip has an access time of 70ns, then TMULT should be set to 0 so that (0*8 + 9)*8 = 72ns
70ns.
· If your flash chip has an access time of 90ns, then TMULT should be set to be 1 so that (1*8 + 9)*8 =
136ns > 90ns.
If you do not set the access time to be greater than the access time of your flash chip, your system will not
operate.
3.1.3 Flash Memory Examples
The following are some ROM_GENERAL_SETTNG examples:
· For one 8 bit flash chip with a 70ns access time, ROM_GENERAL_SETTNG = 0x00000001.
· For one 16 bit flash chip with a 110ns access time, ROM_GENERAL_SETTNG = 0x10000002.
· For two 16 bit flash chips in two banks with a 110ns access times, ROM_GENERAL_SETTNG =
0x1000000A.
· For two 16 bit flash chips in parallel to form a 32 bit data width bank with a 120ns access time,
ROM_GENERAL_SETTNG = 0x10000003.
3.2 SDRAM
The KS8695.S macros listed below define the SDRAM bank data width, number of banks, and number of
column address bits. The demo board uses a 32 bit data width, 4 banks, and 8 column address bits.
#define TMP_SDRAM_REG0 (((SDRAM_BANK_0+SDRAM_BANK0_SIZE-
1)>>16)<<22)|((SDRAM_BANK_0>>16)<<12)|SDRAM_UNM_BANKS4| \
SDRAM_BANK_COLAB8|SDRAM_BANKS_DBW32
#define TMP_SDRAM_REG1 (((SDRAM_BANK_1+SDRAM_BANK1_SIZE-
1)>>16)<<22)|((SDRAM_BANK_1>>16)<<12) | SDRAM_BANK_COLAB8 |
SDRAM_UNM_BANKS4|SDRAM_BANKS_DBW32
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Micrel Application Note 125
#define SDRAM_REG1 (((SDRAM_BANK_1+SDRAM_BANK1_SIZE-
1)>>16)<<22)|((SDRAM_BANK_1>>16)<<12)|SDRAM_UNM_BANKS4|\
SDRAM_BANK_COLAB8|SDRAM_BANKS_DBW32
#define REM_SDRAM_REG1 (((REMAPPED_SDRAM_BANK_1+SDRAM_BANK1_SIZE-
1)>>16)<<22)|((REMAPPED_SDRAM_BANK_1>>16)<<12)|\
SDRAM_BANK_COLAB8 |SDRAM_UNM_BANKS4|SDRAM_BANKS_DBW32
#define SDRAM_REG0 (((SDRAM_BANK_0+SDRAM_BANK0_SIZE-
1)>>16)<<22)|((SDRAM_BANK_0>>16)<<12)|SDRAM_UNM_BANKS4|\
SDRAM_BANK_COLAB8|SDRAM_BANKS_DBW32
#define REM_SDRAM_REG0 (((REMAPPED_SDRAM_BANK_0+SDRAM_BANK0_SIZE-
1)>>16)<<22)|((REMAPPED_SDRAM_BANK_0>>16)<<12)| \
SDRAM_BANK_COLAB8|SDRAM_UNM_BANKS4|SDRAM_BANKS_DBW32
Note: These values are written to registers SDRAM Control Register 0 (SDCON0 Offset 0x4030) and SDRAM
Control Register 1 (SDCON1 Offset 0x4034).
3.2.1 SDRAM Data Width
Modify the macros above to use the constant below denoting the appropriate SDRAM bank data width:
· SDRAM_BANKS_DBW8 denotes 8 bit data width
· SDRAM_BANKS_DBW16 denotes 16 bit data width
· SDRAM_BANKS_DBW32 denotes 32 bit data width
If you use two SDRAM in parallel (meaning both SDRAM chips share the same chip select), then note the
following:
· If you use two 8 bit SDRAM in parallel, then use SDRAM_BANKS_DBW16.
· If you use two 16 bit SDRAM in parallel, then use SDRAM_BANKS_DBW32.
3.2.2 SDRAM Banks
Modify the macros above to use the constant below denoting the appropriate SDRAM number of banks:
· SDRAM_UNM_BANKS2 denotes SDRAM with 2 banks
· SDRAM_UNM_BANKS4 denotes SDRAM with 4 banks
3.2.3 SDRAM Column Address Bits
Modify the macros above to use the constant below denoting the appropriate number of column address bits:
· SDRAM_BANK_COLAB8 denotes 8 column address bits
· SDRAM_BANK_COLAB9 denotes 9 column address bits
· SDRAM_BANK_COLAB10 denotes 10 column address bits
· SDRAM_BANK_COLAB11 denotes 11 column address bits
- File Linux/include/asm-arm/arch-ks8695/platform.h
This file contains many constant and macro definitions used by Linux.
Flash memory configuration information is defined in this file.
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Micrel Application Note 125
4.1 Flash Memory
The platform.h constants and macros listed below define the flash chip size, bank data width, and interleave.
The demo board uses a 4MB size, 8 bit data width, and no interleave.
#define KS8695_FLASH_SIZE 0x00400000
#define CFI_DEVICETYPE CFI_DEVICETYPE_X8
#define CFI_INTERLEAVE 1
#cfi_buswidth_is _1( ) (1)
#cfi_buswidth_is _2( ) (0)
#cfi_buswidth_is _4( ) (0)
#cfi_interleave_is_1() (1)
#cfi_interleave_is_2() (0)
#cfi_interleave_is_4() (0)
4.1.1 Flash Memory Size
Modify the KS8695_FLASH_SIZE constant to use the value below denoting the appropriate flash chip size:
· 0x00400000 denotes 4MB
· 0x00800000 denotes 8MB
Note: A 2MB flash chip size is not a supported option because the BSP requires more than 2MB of flash
memory.
4.1.2 Flash Memory Data Width
Modify the CFI_DEVICETYPE constant to use the constant below denoting the appropriate flash bank data
width:
· CFI_DEVICETYPE_X8 denotes 8 bit data width
· CFI_DEVICETYPE_X16 denotes 16 bit data width
· CFI_DEVICETYPE_X32 denotes 32 bit data width
Modify the cfi_buswidth_is _1, cfi_buswidth_is _2, and cfi_buswidth_is _4 macros to use the values below
denoting the appropriate flash bank data width:
· For an 8 bit data width set the macros as follows:
#cfi_buswidth_is _1( ) (1)
#cfi_buswidth_is _2( ) (0)
#cfi_buswidth_is _4( ) (0)
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· For a 16 bit data width set the macros as follows:
#cfi_buswidth_is _1( ) (0)
#cfi_buswidth_is _2( ) (1)
#cfi_buswidth_is _4( ) (0)
· For a 32 bit data width set the macros as follows:
#cfi_buswidth_is _1( ) (0)
#cfi_buswidth_is _2( ) (0)
#cfi_buswidth_is _4( ) (1)
4.1.3 Flash Memory Interleave
Modify the CFI_INTERLEAVE constant to use the value below denoting the appropriate flash chip interleave:
· 1 denotes one flash chip is used
· 2 denotes two flash chips are used in parallel
· 4 denotes four flash chips are used in parallel
Modify the cfi_interleave_is_1, cfi_interleave_is_2, and cfi_interleave_is_4 macros to use the values below
denoting the appropriate flash chip interleave:
· For one flash chip, set the macros as follows:
#cfi_interleave_is_1() (1)
#cfi_interleave_is_2() (0)
#cfi_interleave_is_4() (0)
· For two flash chips used in parallel, set the macros as follows:
#cfi_interleave_is_1() (0)
#cfi_interleave_is_2() (1)
#cfi_interleave_is_4() (0)
· For four flash chips used in parallel, set the macros as follows:
#cfi_interleave_is_1() (0)
#cfi_interleave_is_2() (0)
#cfi_interleave_is_4() (1)
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Micrel Application Note 125
- File Soho/loader/include/flashMap.h
Flash memory configuration information is defined in this file.
5.1 Flash Memory
The flashMap.h constants listed below define the flash bank data width, interleave, and name. The demo board
uses an 8 bit data width, no interleave, and “AMD29LV033C”.
#define FLASH_DEV_WIDTH 0x8
#define FLASH_DEV_PARALLEL 0x1
#define FLASH_STRING “AMD29LV033C”
5.1.1 Flash Memory Data Width
Modify the FLASH_DEV_WIDTH constant to use the value below denoting the appropriate flash bank data
width:
· 0x8 denotes 8 bit data width
· 0x10 denotes 16 bit data width
· 0x20 denotes 32 bit data width
5.1.2 Flash Memory Interleave
Modify the FLASH_DEV_PARALLEL constant to use the value below denoting the appropriate flash chip
interleave:
· 1 denotes one flash chip is used
· 2 denotes two flash chips are used in parallel
· 4 denotes four flash chips are used in parallel
5.1.3 Flash Memory Name
Modify the FLASH_STRING constant to use the string denoting the appropriate flash chip name.
An example:
· “AMD29LV033C”
- File Soho/loader/linuxloader/Makefile
SDRAM configuration information is defined in this file.
6.1 SDRAM
The Makefile constants listed below define the SDRAM size. The demo board uses a 16MB SDRAM in both
banks.
SDRAM_SIZE_BANK0 = 0x01000000
SDRAM_SIZE_BANK1 = 0x01000000
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Micrel Application Note 125
6.1.1 SDRAM Size
Modify the SDRAM_SIZE_BANK0 and SDRAM_SIZE_BANK1 constants to use the values below denoting the
appropriate SDRAM size:
· 0x00000000 denotes the bank is disabled
· 0x01000000 denotes 16MB
· 0x02000000 denotes 32MB
Some examples:
· For a 16MB SDRAM in both banks, set the constants as follows:
SDRAM_SIZE_BANK0 = 0x01000000 (16MB)
SDRAM_SIZE_BANK1 = 0x01000000 (16MB)
· For a 32MB SDRAM in one bank (i.e. one chip select), set the constants as follows:
SDRAM_SIZE_BANK0 = 0x02000000 (32MB)
SDRAM_SIZE_BANK1 = 0x00000000 (disabled)
Note: An 8MB SDRAM size is not a supported option because the BSP requires more than 8MB of SDRAM.
- Verifying New BSP Configuration
After the appropriate changes have been made to the files described above, rebuild and test the BSP to verify
proper flash memory and SDRAM operation.
Regards,
Christopher.