Dave,
Now that I’ve read over the datasheet of the display, I was wondering how you got 30FPS as the limit.
If you go by the nominal clocking rate of 9MHz you get just shy of 60fps: 9MHz/525/286=59.94fps (includes front/back porch and setup pulse).
Or did you go by the nominal response time of the screen at 30ms which is about 33fps?
The good news for everyone that is new to FPGA’s is the PSP screen is driven in the same manner as a VGA monitor and there are lots of VHDL and Verilog examples on the net to help you along. Implementing a memory controller, hardware sprite generator, and microcontroller interface will be the fun part!
-Bill