Help with USB Differential Impedance on layout

Community PCB Design
1

Hey there,

I’m doing my first layout using USB and was hoping someone could give me some pointer as to calculating the correct line widths and spacing to get the correct differential impedance.

Thanks.

2

The Pulsonix PCB software I use has a calculator for microstrip. What is the thickness of the PCB, and what is the permittivity of the material? Is it multilayer or double-sided?

Leon

3

Hey Leon,

the PCB is bound by BatchPCB’s rules so the thickness is 62mil (1.5748mm), it’s a double-sided board, FR-4 has an Er of 4.5-4.9. Differential impedance should be 90Ohms.

Thanks.

4

I’m trying some of the formulas on the web and I’m getting about 12mil spacing for 20mil widths. Anywhere near?

5

I get 34.2 mils track widths for 20 mils track spacing. The formula is taken from “The Design Guide for Electronic Packaging Utilising High Speed Techniques” IPC-2251 document

Leon

6

Thanks, I’ll have a read and see if I can confirm that. Cheers.

7

Leon, those figures just don’t work for me. I’ll plot out my working and see if we can see what’s going wrong.

I’m working from Eric Bogatin’s Signal & Power Integrity book and he uses the formulas released by Nat Semi in their AN-905 app note as his approximations.

Zo = (87/sqrt(Er+1.41))*ln(5.98H/(0.8W+T))

Zdiff = 2Zo(1-0.48exp(-0.96S/H))

Reordered:

Zo = Zdiff/(2*(1-0.48exp(-0.96S/H)))

W = ((7.475H)/exp((Zosqrt(Er + 1.41))/87)) - 1.25*T

where

S is the microstrip spacing

H is the dielectric thickness

Er is the dielectric permittivity

T is the microstrip thickness (1.4 mil for 1oz copper)

W is the microstrip width.

Using your numbers I get a Zo of 91.7Ohms and a Zdiff of 118Ohms. I’m using T=1.4, Er=4.5, H=62.

If I work backwards from our target 90 Ohm Zdiff, using the minimum spacing of 8 mils and the height H of 62 mils, I get a required Zo of 78 Ohms.

If I then plug in this value to the Zo formula above I can solve for W, I get ~51 mils.

Does that make sense? Have I done anything wrong? My reasoning for using the minimum of 8 mil spacing is that as the spacing goes up, any impedance reduction from coupling is lost meaning that the characteristic impedance of each single ended microstrip would need to be less to meet the differential impedance. By minimising the spacing I therefore minimise the width of my microstip.

Shareef (who could be talking absolute tosh).

[Edit - wrong value in one of the formulas above. Now corrected. Also put reordered formula for Zo and W calculation.]

8

The Pulsonix calculator uses the same formulae, so you should get the same numbers.

9

Well I don’t, that’s the point. :slight_smile:

Anybody else with any input?

10

Well, it seems I can’t use a calculator but I still don’t get the values you came out with.

Using your values, I now get a Zo of 69.46 Ohms. This leads to a track width of 64 mils which seems excessive. By reducing the spacing to 8 mils as I did in my calculations the width comes down quite a bit.

I’m going with 50 mils width and 8 mil spacing unless someone can point out where I’ve gone wrong.

11

I checked my values with this calculator:

http://www.technick.net/public/code/cp_ … strip_diff

and get the correct differential impedance (116 ohms). You should recheck your calculations.

12

Ah, see now we’re getting somewhere. Why are you calculating for 116 Ohms instead of 90 Ohms?

In my post above I calculated your Zdiff to be 118 Ohms, which is close enough, so at least we know my maths is ok.

Shareef.

13

I checked the USB requirements and I got it wrong. The differential impedance should be 90 ohms, and the impedance of each track to ground should be 30 ohms. I don’t think that is achievable with a double-sided board, buried microstrip will be needed.

14

I wouldn’t worry too much about the impedance not being exact, expecially if the tracks are fairly short, and you are not running at the full USB 2.0 speeds. There are plently of commercial products that have USB, and only use a double-layer PCB.

15

Leon, thanks for that. Good to have you checking that for me. Appreciate your help.

Michael, the tracks are short but I will be running at the hi-speed data rates so it was important to get it right. Even if it was only a learning exercise it would still have been useful. One of the reasons I was concerned is that I have two dev boards in front of me that use the PHY I will be using. Both are double sided boards, made by the same manufacturer, but they have different trace widths. One is about 20 mils and the other 30 mils. Nowhere near the 50 I calculated.

Ah well, I’ll see if it works when I power the board up for the first time. I’ve probably got GND and VCC the wrong way round having spent so much time on this… :smiley: