I am designing a USB hub as a step before a bigger project I have in mind. The Hub chip’s application notes talk about a differential impedance of 90ohms on the USB data pair traces.
How critical is this, and how would I best go about implementing it? I am not really too sure about microstrips, and with the two sets of figures mentioned on a 4-layer PCB the optimal trace width is 7mil ± 0.5mil which is below the BatchPCB minimum, and on a 2-layer board the optimal trace width jumps to 60mil which I think is rather thick.
You’ll find several calculators for microstrip design with Google. You need to know the electrical characteristics and thickness of the PCB board material you are using; FR4, presumably. Your PCB supplier should be able to give you the data.
A 0.1" track over a groundplane has a characteristic impedance of about 50 ohms.
It won’t matter too much if the connections are kept very short. If you are making a commercial product, I’d stick with the recommendations, otherwise you will find that your product simply doesn’t work in some situations: high-speed USB is quite fussy about signal integrity.
So… track length is irrelevant (since the microstrip calculations mention nothing about length, just thickness), it’s basically all to do with the width of the track.
I used the calculator [here (it’s in metric but I converted the figures from inch to mm)
FR4 has an Er of 4.2
The BatchPCB service uses 0.062" thick board (1.5748mm)
1oz copper is 0.0014" thick (0.03556mm)
and a trace width of 0.97mm gives me an impedance of 90.04ohms which is well inside the ± 10% tolerance allowed.
Thanks for the tips, I have tried a few test layouts in eagle using the 38.189mil trace width and it gets rather interesting when I get to the 8mmx8mm 56-lead QFN package. It’s pads are about 9mil wide, so I try to neck it down to 8mil as close as I can to the chip, and keep the length of the small section as short and equal length as I possibly can, which isn’t too easy when I got Vcc and GND pins mixed in the same area that want decoupling caps.
With a 4-layer PCB the 90ohm traces get much thinner, close to 8mil but I really don’t want to move up to 4-layer. Also I haven’t found any info on the spacing of the inner layers of the boards from BatchPCB. When I do the boards for my larger project I will be using 4-layers so having the smaller traces will be a handy bonus.
Sorry if you already realize this but differential impedance and characteristic impedance are different. They don’t seem to mention the characteristic impedance in that app note so I’m not sure if its important other than as a parameter used to calculate the differential impedance.
Basically the spacing between the two tracks is important too, not just the width. You’ll need to google for a differential impedance calculator.
So if each trace on its own is 50 Ohms (W=~112 mils) then the calc below says they should be around 96 mil apart for a 90 Ohm differential impedance.
IF I’m understanding this right, then 50 mil traces separated by 10 mils should be about 90 Ohms differential impedance. I’ve seen different numbers (wavelength/10, /20, /30) for how long traces need to be before it matters, but these should be longer than the fan down to the chip pins.
Edit: This document says both traces should each be 45 ohms: