Hi everyone, I’m looking for some technical feedback on an I2C network I’m designing.
I want to build an I2C bus using the P82B96 bus extender. The topology will feature several ‘T-junction’ sections. At each junction, I plan to have a smart I2C master/slave node performing various tasks.
My specific question concerns the T-splitter design. I am considering placing two P82B96 chips back-to-back (as shown in my diagram) to extend the bus in both directions while tapping off a local signal. I haven’t been able to find any reference designs or diagrams where this has been done before.
My assumption is that since the Sx/Sy side acts as a standard I2C interface, this configuration should work. Is this correct? Can I safely use two P82B96 chips back-to-back to create this network?
Thanks in advance for your help!
Fig1
I received commends on this Fig1 architecture and this architecture is not allowed. The data sheets show that combining Sx/Sy is not supported.
Below fig 2 my second proposal to see if this is correct. Technicaly it’s now a muti point architecture and based on what I read this is allowed, Let me know in the commends what you think.
Fig2