P1.31 - sampled on reset. If low JTAG port is disabled
P1.20 - sampled on reset. If low enable P1.16:25 to operate as Trace port
P1.26 - sampled on reset. If low enables P1.26:31 to operate as debug port
Does the state of these pins affect whether JTAG works or not?
Right now I only connect P0.14 to GND to allow programming (for both serial and JTAG). I am not doing anything with P1.20, P1.26, or P1.31 right now.
8-Dale[/quote]
YES, those pins do matter, for your LPC-2148 Proto Board.
P1.31 is the JTAG nTRST signal and will be handled by your JTAG debugger.
P1.20 does not really matter for your USB OCD Tiny since it does not function with the TracePort. It should be high during reset, so that you can use those pins for your own functions.
P1.26 is the JTAG RTCK signal which must be sampled low on reset, or the NXP bootloader will disable the JTAG pins. On your LPC-2148 Proto Board that is handled by the DBG_E jumper. The jumper should be installed if you want to use the JTAG port for a debugger or FLASH programmer.
P0.14 is the BSL signal which is controlled by the ICSP DIP switch on your LPC-2148 Proto Board. It is not related to the JTAG pins, but it does cause the NXP bootloader to disable the startup of your user code and remain in bootloader mode. It will NOT enable the JTAG pins. The JTAG pins are controlled by the DBG_E jumper.
dshuman:
P1.31 is the JTAG nTRST signal and will be handled by your JTAG debugger.
OK, good. I hopefully don't have to worry about this then.
dshuman:
P1.26 is the JTAG RTCK signal which must be sampled low on reset, or the NXP bootloader will disable the JTAG pins. On your LPC-2148 Proto Board that is handled by the DBG_E jumper.
OK, DBG_E was already installed.
dshuman:
P0.14 is the BSL signal which is controlled by the ICSP DIP switch on your LPC-2148 Proto Board. It is not related to the JTAG pins, but it does cause the NXP bootloader to disable the startup of your user code and remain in bootloader mode. It will NOT enable the JTAG pins. The JTAG pins are controlled by the DBG_E jumper.
Does having P0.14 grounded affect whether JTAG works or not? I have been having it grounded for both serial programming and JTAG (which has never worked right and doesn't work at all now).
This is looks like I have a bad JTAG unit, which means it was bad when I got it. It never worked right, but I didn’t know it because I am just learning the ARM stuff. I will have to call SFE and get an RMA for the unit so I can get it replaced.
leon_heller:
If you are using JTAG bootloading should be disabled. See page 295 of the User Manual.
Leon
What version of the LPC2148 UM are you refering to? Version 2 does not say anything about prohibiting JTAG use with P0.14 low on page 295. Of course, actual code debugging would be useless if P0.14 was low at reset because of the memory remapping, but the memory remapping can be switched to the user map via JTAG. The bootloader flow chart indicates that the JTAG interface is enabled before P0.14 is checked if CRP is not enabled, which seems to indicate that NXP did not intend mutual exclusivity?
One valid reason for using JTAG with P0.14 low might be to recover from defective user code that unintentionally disables the JTAG interface or misprograms the PLL in such a way that execution stops in user mode, among other things. The memory remapping can be set to the user map via JTAG and then the FLASH can be erased. If your circuit also has a serial port, the same could be accomplished via the serial port ISP, but if you do not have a serial port then recover is still possible using JTAG by booting into ISP mode. Other than something like that I can’t think of any other reason that anyone would want to us JTAG when booting into ISP mode, but I have not seen any documentation warning against it?
linuxguy:
Does having P0.14 grounded affect whether JTAG works or not? I have been having it grounded for both serial programming and JTAG (which has never worked right and doesn’t work at all now).
According to the ISP flowchart in the manual, P0.14 will not affect whether JTAG is enabled or not. In fact, the criteria for enabling the JTAG interface are processed before P0.14 is sampled by the bootloader. However, you should not try to debug your code when starting in ISP mode because ISP alters the memory map. Your vector tables will be unavailable, until the memory mapping is changed to a user memory map in the MEMMAP register.