Coyote973:
O.K. I took a look on your code and I have to say that is much different than the original, so I don’t understand much, but I would like to ask you some questions:
-
Have you implemented a buffer ( like cache) that temporarily stores data during the write process? (I mentioned in earlier posts that this is essential)
-
I have tried in mode 2 with 10 channels and sampling freq 10kHz, the device did not answer any error ( buffer overrun), but it surely cannot write such speeds.
-
How can I add in the MODE2ISR() routine a simple counter which increases every interrupt and writes on the card, instead of ADC channels. In this way it could be possible to test the maximum writing speed.
-
See files buffer.c and buffer.h The #defines in buffer.h set the buffer size and number. Don’t get so carried away that you don’t leave space in the 32K of RAM for things like stacks and the other data.
-
I have tested mode 2 to 90,000 SPS (10 channels at 9,000Hz) with no trouble. If there is no space in the buffer, new data is dropped so for testing in mode 2 I used a simple program to scan for the ‘$’ marker in the data file. Grounding the inputs helps a lot for this:
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
main(int argc, char **argv)
{
int i, c, lastchar;
int val;
int length;
int mode = 0;
length = 10;
if(argc == 2)
{
fprintf(stderr, "%s", argv[1]);
length = atoi(argv[1]);
if(length < 1 || length > 10)
{
fprintf(stderr, "Data length parameter out of range: %d\n", length);
exit(1);
}
}
lastchar = 0;
i = 0;
length = length * 2 + 2;
while( (c = getchar()) != EOF)
{
i++;
if(mode == 0)
{
if(c == '
- The mode 2 code is replaced with the simple program you are looking for if you define TESTSD. It also checks for buffer over run and marks the next buffer. This is scanned by:
#include <stdio.h>
main()
{
long offset;
int i, c, count;
count = offset = 0;
while( (c = getchar()) != EOF)
{
offset++;
if(count == 4)
{
if(offset % 512)
continue;
else
count = 0;
}
switch(c)
{
case 0xde:
count = 1;
break;
case 0xad:
if(count == 1)
count++;
else
count = 0;
break;
case 0xbe:
if(count == 2)
count++;
else
count = 0;
break;
case 0xef:
if(count == 3)
{
count++;
printf("%04x\n", offset/512);
}
else
count = 0;
break;
default:
count = 0;
}
}
}
I measured about 400KB/sec write speed. This decreases when running the ADC because not all of the CPU cycles are available to the data storage code. && lastchar == ’
3) The mode 2 code is replaced with the simple program you are looking for if you define TESTSD. It also checks for buffer over run and marks the next buffer. This is scanned by:
§DISCOURSE_HOISTED_CODE_1§
I measured about 400KB/sec write speed. This decreases when running the ADC because not all of the CPU cycles are available to the data storage code.)
{
mode = 1;
i = 0;
}
}
else
{
if(i == length)
if(c == '
- The mode 2 code is replaced with the simple program you are looking for if you define TESTSD. It also checks for buffer over run and marks the next buffer. This is scanned by:
§_DISCOURSE_HOISTED_CODE_1_§
I measured about 400KB/sec write speed. This decreases when running the ADC because not all of the CPU cycles are available to the data storage code. && lastchar == ’
3) The mode 2 code is replaced with the simple program you are looking for if you define TESTSD. It also checks for buffer over run and marks the next buffer. This is scanned by:
§DISCOURSE_HOISTED_CODE_1§
I measured about 400KB/sec write speed. This decreases when running the ADC because not all of the CPU cycles are available to the data storage code.)
{
i = 0;
putchar('\n');
}
else
mode = 0;
else if((i&1) == 0)
{
val = ((lastchar << 8) | (c & 0xff))&0x3ff;
printf("%d ",val);
}
}
lastchar = c;
}
}
- The mode 2 code is replaced with the simple program you are looking for if you define TESTSD. It also checks for buffer over run and marks the next buffer. This is scanned by:
§_DISCOURSE_HOISTED_CODE_1_§
I measured about 400KB/sec write speed. This decreases when running the ADC because not all of the CPU cycles are available to the data storage code.
