LPC2388 Interrupt Enabling-Disabling in Time Critical System

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1

I m working on a time critical system on LPC2388.

Earlier I worked on PIC18. Here, for a bit of time critical process, I have disabled the hardware interrupts and later enabled them. If a hardware interrupt is given, particular interrupt flag is set but it is not served until the interrupts are enabled. When the interrupt is enabled, because the flag is already set it will then serve the interrupt.

I put this more clearly…

for (10 iterations)

{

interrupt disabled

statements1

statements2

statements3

statements4

statements5

interrupt enabled

}

Suppose an interrupt is given in the 5th iteration during statement3 by pressing a push button, the corresponding flag is set but it is not served because the interrupt is disabled before statement1. After the statement4 & statement5 are executed, when the interrupts are enabled, because the flag is already set, now the interrupt is served and when it returns, this “for” loop continues.

I could see the above process clearly happen in Proteus when working on PIC18. As Proteus doesn’t has support for LPC2388, I m skeptical about this. I know EXTINT register contains the flags.

So, Can this be done in LPC2388 too??

2

I don’t know ARM7, but I have some experience with Cortex M3 and PIC18.

The NVIC of the Cortex controllers is much more standardized then the ARM7 ones.

Every vendor dit it a little different. Seems you can’t circumvent reading the LPC2388

reference manual carefully, especially the the VIC part, and that of the interrupt-generating

peripheral.

However, few controllers have such crappy interrupt support like the PIC18.

The LPC2388 has 32 separate int-vectors, so you don’t need to browse through the flags

just to see what happened.

It is certainly possible with the LPC2388, but ‘slighty’ more complex to understand and configure.

3

Thank you Frame.