Im looking for a way to test if there is an interrupt currently processing on my ARM7. I can see that the interrupt disable bits are set to disable the FIQ and IRQ interrupts, but are they set when an interrupt is triggered? In my “TMS470R1x User’s Guide” in the section on Exceptions, it gives a run down when an exception occurs and it says it “may also set interrupt disable flags” but nothing decisive.
My question is: Do the CPSR I and F bits signify there is an interrupt in progress, i.e, when an interrupt occurs, is the disable flag set? If not, how could I determine if there is an interrupt in progress?
Typically interrupts cause a context switch, jump directly to the interrupt code, process the interrupt, and return (context switch back). Interrupts don’t run simultaneously (unless you have a multi-core system). So that pretty much means unless your software interrupts the interrupt (nested interrupts) the interrupt will start, process, and finish before your testing code ever gets run.
Also depending on what processor you are using, you may have a prioritized interrupt processor. That means a higher priority interrupt may interrupt a lower priority one, but not the other way around.
Interrupts are get-in and get-out code, boiling it down to basics, your user code should never know when its being interrupted.