Main clock problem (oppenocd,usbjtag)

Development Boards MicroMod
1

i am use openocd with usb jtag based on ft2232 board layout usbjtag

and my mini arm modul with at91sam7s256

comunication betwen arm and pc via jtag seems to be ok

jtag chain communication without problem

if i write command flash info 0 chip was detected but master clock is 0 kHZ WHY??

> flash info 0
#0: at91sam7 at 0x00100000, size 0x00040000, buswidth 4, chipwidth 0
        #0: 0x00000000 (0x40000 256kB) protection state unknown

at91sam7 information: Chip is AT91SAM7S256
cidr: 0x270d0940, arch: 0x0070, eproc: ARM7TDMI, version:0x000,  flashsize: 0x00040000
master clock(estimated): 0kHz
pagesize: 256, lockbits: 16 0x0000, pages in lock region: 64
securitybit: 0,  nvmbits(2): 0x0

why master clock is zero ?

why protection state is unknown ?

What is the reason of this ??

I use openocd ver Open On-Chip Debugger 1.0 (2008-05-04-17:13) svn:640

i have this my jtag http://www.at91.com/repFichier/Project-355/scheme.png

and this my board http://www.at91.com/repFichier/Project- … _modul.png

2

miroslav.talasek:
i am use openocd with usb jtag based on ft2232 board layout usbjtag

and my mini arm modul with at91sam7s256

comunication betwen arm and pc via jtag seems to be ok

jtag chain communication without problem

if i write command flash info 0 chip was detected but master clock is 0 kHZ WHY??

> flash info 0

#0: at91sam7 at 0x00100000, size 0x00040000, buswidth 4, chipwidth 0
#0: 0x00000000 (0x40000 256kB) protection state unknown

at91sam7 information: Chip is AT91SAM7S256
cidr: 0x270d0940, arch: 0x0070, eproc: ARM7TDMI, version:0x000, flashsize: 0x00040000
master clock(estimated): 0kHz
pagesize: 256, lockbits: 16 0x0000, pages in lock region: 64
securitybit: 0, nvmbits(2): 0x0




why master clock is zero ?

why protection state is unknown ?

What is the reason of this ??

I use openocd ver Open On-Chip Debugger 1.0 (2008-05-04-17:13) svn:640



i have this my jtag [http://www.at91.com/repFichier/Project-355/scheme.png](http://www.at91.com/repFichier/Project-355/scheme.png)

and this my board [http://www.at91.com/repFichier/Project- ... _modul.png](http://www.at91.com/repFichier/Project-355/arm_modul.png)

I have the same problem, but I’m working with AT91SAM7XC256, and the last version of openocd 985.

I don’t believe these are stupid problems, and taking into account that the openocd documentation is very poor, I guess this is the reason why forums like this exist

Why nobody try to give some answers for above questions ?
I suppose we have some developers here …

If you are a newbie in using openocd then you are lost…

Then why this forum exist ?

If you don’t want to be disturbed by some stupid newbie question then why you just don’t close this forum for persons like me and a make the access based on invitations!

Atlas

3

After digging inside the code it seems that if you have an external oscillator openocd is not capable of calculating the main clock frequency. This is also my case.

This piece of code is taken from at91sam7.c file.

Lets take a look at case 1 and 3, in both cases the frequency is calculated only if MAINRDY bit is set, but in case of external oscillator this bit is disabled.

I believe is necessary to add a new parameter in config file, to specify the external clock value.

I’ll try to add a patch and see if is working

	at91sam7_info->mck_valid = 0;
	switch (mckr & PMC_MCKR_CSS) 
	{
		case 0:			/* Slow Clock */
			at91sam7_info->mck_valid = 1;
			mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
			tmp = mainfreq;
			break;
		case 1:			/* Main Clock */
			if (mcfr & CKGR_MCFR_MAINRDY) 
			{
				at91sam7_info->mck_valid = 1;
				mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
				tmp = mainfreq;
			}
			break;

		case 2:			/* Reserved */
			break;
		case 3:			/* PLL Clock */
			if (mcfr & CKGR_MCFR_MAINRDY) 
			{
				target_read_u32(target, CKGR_PLLR, &pllr);
				if (!(pllr & CKGR_PLLR_DIV))
					break; /* 0 Hz */
				at91sam7_info->mck_valid = 1;
				mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
				/* Integer arithmetic should have sufficient precision
				   as long as PLL is properly configured. */
				tmp = mainfreq / (pllr & CKGR_PLLR_DIV) *
				  (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
			}
			break;
	}