MSP430F5437 with 16MHz XT1

Development Boards MicroMod
1

I’m having trouble setting up the MSP430F5437 to run from a 16MHz master clock. (It’s my first time working on MSP programming from scratch, and we havent used the 500 series chips before.)

I have a 16MHz crystal connected to XT1 with external caps. Other than that, there are no other external components being used in the code yet. We also have a 4MHz crystal available but need the master clock to run at 16MHz to write to an SRAM chip fast enough. Are there some obvious mistakes in my coding?

I got the SetVCoreUp function from the MSP430x5xx User guide although what’s curious to me here is that the sample TI code for a 12MHz DCO does not change the core voltage but the user guide says you must change the core voltage. (The datasheet shows 16MHz in the third range and 12MHz in the second voltage range)

With the following code, it gets stuck in the loop waiting for XT1 to stabilize. OFIFG keeps being set due to the DCOFFG in UCSCTL7 being set. Furthermore, this is caused by the DCO bits in UCSCTL0 are set to 0x31.

Any Help would be much appreciated,

Thanks

main.c :

#include “msp430x54x.h”

void SetVCoreUp (unsigned int level)

{

// Open PMM registers for write access

PMMCTL0_H = 0xA5;

// Set SVS/SVM high side new level

SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;

// Set SVM low side to new level

SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;

// Wait till SVM is settled

while ((PMMIFG & SVSMLDLYIFG) == 0);

// Clear already set flags

PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);

// Set VCore to new level

PMMCTL0_L = PMMCOREV0 * level;

// Wait till new level reached

if ((PMMIFG & SVMLIFG))

while ((PMMIFG & SVMLVLRIFG) == 0);

// Set SVS/SVM low side to new level

SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;

// Lock PMM registers for write access

PMMCTL0_H = 0x00;

}

int main( void )

{

volatile unsigned int i;

// Stop watchdog timer to prevent time out reset

WDTCTL = WDTPW + WDTHOLD;

SetVCoreUp(1);

SetVCoreUp(2);

P1DIR |= BIT0; // P1.0 output

P8DIR |= 0x20; //P8.5 is pulse for solenoid.

P8DIR |= 0x40; //P8.6 is buzz

P2DIR |= 0x01; //output MClk for debug

P2SEL |= 0x01;

P11SEL |= BIT0; // P11.0 to output ACLK

P7SEL |= 0x03; // Select XT1

UCSCTL2 = FLLN0;

UCSCTL6 = XTS + XT2OFF +XT1DRIVE_2; // HF mode

UCSCTL6 &= ~(XT1OFF); // XT1 On

UCSCTL4 |= SELS_0 + SELM_0; // SMCLK=MCLK=XT1

__bis_SR_register(GIE);

// Loop until XT1 & DCO stabilize

do

{

UCSCTL7 &= ~(XT1HFOFFG +XT1LFOFFG + XT2OFFG + DCOFFG);

// Clear XT2,XT1,DCO fault flags

SFRIFG1 &= ~OFIFG; // Clear fault flags

for(i=0;i<0xFFFF;i++); // Delay for Osc to stabilize

}while (SFRIFG1&OFIFG); // Test oscillator fault flag

__no_operation();

while(1)

{

P8OUT ^= BIT6;

for(i=500;i>0;i–); // Delay (50000~= 37ms… 40Hz…

}

//return 0;

}

2

Hi Mark,

I’m having similar problems with an F5438. I can get past the clock settling but for some reason the uc does not use the full potential of the oscillator I hooked up. A quick check with a scope revealed the oscillator was running at 14 MHz (which is correct). But when running a simple test loop like yours I end up with roughly 56 clock cycles per loop increment. Which is ridiculous. So my system is running somewhere halfway 32 kHz and 14 MHz. Weird.

Have you had any luck with your problem?

I used your Vcore set routine without problems BTW.

Regards,

Sytse.

3

well we have the XT1 going to the crystal on the board layout and using XT2’s pins for some other stuff… BUT… I pulled off a chip temporarily and some resistors that were going to XT2’s pins and wired the crystal to there and ran the msp430x54x_UCS_8.c (modified with correct pins for the 5437) example and it works at 16MHz. I do not know what is up with the vcore it tells you in the user guide you have to set it with a function like I had tried before and is in the OP (???). The example program works though with XT2. My problem is then I tried again what I had done before of modifying that example to work with XT1 in HF mode and it still gets stuck in the stabilization loop.

I’ll post the code / changes I made for XT1 later today. Maybe there’s something small I’m missing to setup it for with XT1.

I had to move on past it for now and have not tried other things past that yet. We can do a mod to swap where the crystal goes but that means cutting the board traces and 4 jumper wires ;'( I’d rather not do that.

4

Here is the working code using XT2 with the 16MHz crystal (modified the example code for the 5437’s pins):

I can see a 16MHz square wave at P2.0.

You said you looked from the test loop and saw clock cycles per loop increment – Did you output your MCLK and observe what the MCLK was actually running at?

//******************************************************************************
//  MSP430F54x Demo - XT2 sources MCLK & SMCLK
//
//  Description: This program demonstrates using XT2 to source MCLK. XT1 is not
//  connected in this case.
//
//  By default, LFXT1 is requested by the following modules:
//     - FLL
//     - ACLK
//  If LFXT1 is NOT used and if the user does not change the source modules,
//  it causes the XT1xxOFIFG flag to be set because it is constantly looking
//  for LFXT1. OFIFG, global oscillator fault flag, will always be set if LFXT1
//  is set. Hence, it is important to ensure LFXT1 is no longer being sourced
//  if LFXT1 is NOT used.
//  MCLK = XT2
//
//               MSP430F5437
//             -----------------
//        /|\ |                 |
//         |  |                 |
//         ---|RST              |
//            |            XT2IN|-
//            |                 | HF XTAL (455kHz - 16MHz)
//            |           XT2OUT|-
//            |                 |
//            |            P2.0 |--> MCLK = XT2
//            |            
//
//   M Smertneck / W. Goh
//   Texas Instruments Inc.
//   September 2008
//   Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B
//
//   Mark W -- Edited for MSP4305437
//   February 2009
//******************************************************************************

#include "msp430x54x.h"

void main(void)
{
  unsigned int i;

  WDTCTL = WDTPW + WDTHOLD;                 // Stop watchdog timer

  P2DIR = BIT0; //P2.0 to output direction
  P2SEL = BIT0; //P2.0 to output SMCLK, MCLK
  
  P5SEL |= 0x0C;                            // Port select XT2

  UCSCTL6 &= ~XT2OFF + XT2DRIVE_1;                       // Enable XT2 even if not used
  UCSCTL3 |= SELREF_2;                      // FLLref = REFO
                                            // Since LFXT1 is not used,
                                            // sourcing FLL with LFXT1 can cause
                                            // XT1OFFG flag to set
  UCSCTL4 |= SELA_2;                        // ACLK=REFO,SMCLK=DCO,MCLK=DCO

  // Loop until XT2 & DCO stabilize
  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
    for(i=0;i<0xFFFF;i++);                  // Delay for Osc to stabilize
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

  __no_operation();

  UCSCTL4 |= SELS_5 + SELM_5;               // SMCLK=MCLK=XT2

  while(1);                                 // Loop in place
}

AND… here is the code I modified back to use XT1 in HF. It has commented out anywhere that was XT2 specific and added in code for XT1. This gets stuck in the stabilization loop with the fault flag always getting set again. I set XT1 on, set it to HF mode, set its drive level, and then cleared the XT1HFOFFG flag in the stabilization loop. Is there any step for XT1 I missed there? My impression was XT1 set to HF mode “should” work exactly like XT2…

//******************************************************************************
//  MSP430F54x Demo - XT2 sources MCLK & SMCLK
//
//  Description: This program demonstrates using XT2 to source MCLK. XT1 is not
//  connected in this case.
//
//  By default, LFXT1 is requested by the following modules:
//     - FLL
//     - ACLK
//  If LFXT1 is NOT used and if the user does not change the source modules,
//  it causes the XT1xxOFIFG flag to be set because it is constantly looking
//  for LFXT1. OFIFG, global oscillator fault flag, will always be set if LFXT1
//  is set. Hence, it is important to ensure LFXT1 is no longer being sourced
//  if LFXT1 is NOT used.
//  MCLK = XT2
//
//               MSP430F5438
//             -----------------
//        /|\ |                 |
//         |  |                 |
//         ---|RST              |
//            |            XT2IN|-
//            |                 | HF XTAL (455kHz - 16MHz)
//            |           XT2OUT|-
//            |                 |
//            |            P2.0 |--> MCLK = XT2
//            |            
//
//   M Smertneck / W. Goh
//   Texas Instruments Inc.
//   September 2008
//   Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B
//
//   Mark W -- Edited for MSP4305437
//   February 2009
//******************************************************************************

#include "msp430x54x.h"

void main(void)
{
  unsigned int i;

  WDTCTL = WDTPW + WDTHOLD;                 // Stop watchdog timer

  P2DIR = BIT0; //P2.0 to output direction
  P2SEL = BIT0; //P2.0 to output SMCLK, MCLK
  
//  P5SEL |= 0x0C;                            // Port select XT2
  P7SEL |= 0x03;                            // Port select XT1
  
//  UCSCTL6 &= ~XT2OFF + XT2DRIVE_1;                       // Enable XT2 even if not used
  UCSCTL6 &= ~XT1OFF + XT1DRIVE_1 + XTS;                  
  UCSCTL3 |= SELREF_2;                      // FLLref = REFO
                                            // Since LFXT1 is not used,
                                            // sourcing FLL with LFXT1 can cause
                                            // XT1OFFG flag to set
  UCSCTL4 |= SELA_2;                        // ACLK=REFO,SMCLK=DCO,MCLK=DCO

  // Loop until XT1 & DCO stabilize
  do
  {
    UCSCTL7 &= ~(XT2OFFG + +XT1LFOFFG + XT1HFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
    for(i=0;i<0xFFFF;i++);                  // Delay for Osc to stabilize
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

  /*// Loop until XT2 & DCO stabilize
  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
    for(i=0;i<0xFFFF;i++);                  // Delay for Osc to stabilize
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag
  */
  
  __no_operation();

  UCSCTL4 |= SELS_0 + SELM_0;               // SMCLK=MCLK=XT1

  while(1);                                 // Loop in place
}
5

No one else has experience with XT1 in HF mode?