MSP430x4xx - FLL clock generation stability

IDE and Software details:

IAR Workbech MSP430

MCU: MSP430FE427

Board 1: http://www.sparkfun.com/commerce/produc … ucts_id=52

Board 2: http://www.ghielectronics.com/details.php?id=1&sid=2

I am using the 32Khz clock through the FLL to generate an 8Mhz clock (recommended maximum).

I use the following lines of code to generate my 8 Mhz:

// 8 Mhz

SCFI0 |= FN_3; // Set DCO operating range

SCFQCTL = 122; // (121+1) x 32768 x 2 = 7.99 Mhz

FLL_CTL0 = DCOPLUS + XCAP14PF; // DCO+ set so freq = xtal x D x N+1

At these settings, my clock signal on the scope seems to change between 8.06 Mhz and 8.13 Mhz. Is this typical?

I am trying to maintain a very stable clock which can be used by the UART module. The UART module has to operate at 921600 b