Olimex ARM-JTAG cable schematic

Development Boards MicroMod
1

Does anyone have a schematic of the Olimex ARM-JTAG cable?

I’m looking for a schematic of this specific cable, not just any other Wiggler clone.

I have such a cable but I’m having a lot of trouble to get it recognised by OCDRemote. It only seems to work at the very lowest speed. My cable has a pin8-to-pin15 connection. I plan to make this cable work with open-source ARM-JTAG debugging software, but in order to do so I want to know exactly how the hardware is configured.

From my own experiments so far, the cable only seems to work when bits 4 and 7 of the data bus are high. I think bit 4 carries the nTRST signal, but what is the purpose of bit 7? (power/enable?) Also there seems to be some return signal on the ‘selected’ parallel port pin, but it’s not clear to me yet what JTAG signal it represents.

So, Olimex, can you release the schematics? Or at least a technical document that describes which signal does what?

2

DB25.2 → INVERSE → JTAG.15 (NTRST)

DB25.3 → JTAG.7 (TMS)

DB25.4 → JTAG.9 (TCK)

DB25.5 → JTAG.5 (TDI)

DB26.6 → JTAG.3 (TRST)

DB26.9 → VCC for the Level shifter i.e. JTAG enable/disable

DB25.11 ← JTAG.13 (TDO)

DB25.13 ← Target VCC sense (only when JTAG is enabled i.e. DB26.9 = 1)

this is the information you need to develop your driver, by the way there is already open source RDI 1.51 compliant DLL for ARM-JTAG at http://twentyone.blogchina.com/ with RDI interface it could be connected to GDB, Keil, IAR, STD, ADS etc debuggers which have RDI support

Tsvetan

3

Great, thanks for the info!

The open source project I was talking about, is OpenOCD.

I’ll have a look too at the H-JTAG project you mentioned.