I fabricated my first PCB board(one sided) through OSH park and used trace width of 20 mil for power traces and 10 mil for all others. When i check the circuit with dc input voltage (ex:50 mv- 600 mv) everything is perfect.
When i connect it to a real input (also a dc potential in the same range, ~30 uA current), the circuit receive signal much lower than original.Other parts of the circuit are working fine, just i am receiving very low signal as soon as it is connected to circuit input.
Can it be due to the trace width. Or if you have any other idea or suggestion please help.
NB: I wanted to upload image of layout and circuit. but can not find attachment option.
Can you please check my following PCB layout. this is my first one. I already fabricated but it did not work(detail I posted in “PCB circuit problem” thread). I would like to order again. So can you please confirm whether there is any problem with my layout.
What exactly are you connecting this to? What’s the “real input”? What is its impedance? Signal type? Required frequency response?
Trace width wouldn’t cause such a problem, unless you are counting on controlled imedances. I’d use wider power traces myself as you do have more than enough board space. It would lower the inductance. I’d also route them from the power connector to the capacitor first and then the IC. You are showing electrolytic caps on your board; are you using them or ceramics? If they are 'lytics, I’d add a parallel 100n ceramic cap to each power rail, and locate them right next to the power pins.
As for layout, I see two issues:
Your traces are leaving the pads at odd (often acute) angles. They should leave perpendicular (or radially for round pads) to avoid acid traps
It looks like there may be some issues between the square pads and the ground pour; ideally the antipad should also be square.
Stylistically, I’d rotate all of the reference designators to face the same direction, make sure they don’t overlap pads (like C4) and add names to the pins on the connectors. I’d also add a board name, revision or date, and some mounting holes.
So some caps (tantalum, some electrolytic) have a polarity assigned to them. Your footprint shows a polarity, but your schematic does not (bad practice). It seems like you are using J1 for your power and you have a decoupling cap on both supplies. The positive end of the caps seem to be connected to your supplies, Vpos and Vneg, with the other end to ground. When you have a negative supply connected to the positive end of the cap (because Vneg is a lower polarity than ground), they can behave as a short or be damaged, Sparkfun actually did a video about this : http://www.youtube.com/watch?v=sW0a9d_vWoc
n1ist:
What exactly are you connecting this to? What’s the “real input”? What is its impedance? Signal type? Required frequency response?
Trace width wouldn’t cause such a problem, unless you are counting on controlled imedances. I’d use wider power traces myself as you do have more than enough board space. It would lower the inductance. I’d also route them from the power connector to the capacitor first and then the IC. You are showing electrolytic caps on your board; are you using them or ceramics? If they are 'lytics, I’d add a parallel 100n ceramic cap to each power rail, and locate them right next to the power pins.
As for layout, I see two issues:
Your traces are leaving the pads at odd (often acute) angles. They should leave perpendicular (or radially for round pads) to avoid acid traps
It looks like there may be some issues between the square pads and the ground pour; ideally the antipad should also be square.
Stylistically, I’d rotate all of the reference designators to face the same direction, make sure they don’t overlap pads (like C4) and add names to the pins on the connectors. I’d also add a board name, revision or date, and some mounting holes.
/mike
Thanks a lot Mike for very detailed reply. Clearly I need to learn a lot!!!
My input range is ± 400 mv. The impedance is around ~4k ohm… Its measurement of a solution taken vs two leads/electrode. Similar to battery cell.
So, connecting Capacitor before IC would reduce noise??? I mean how would this improve, can you explain please.
I am actually using Ceramic.
So you mean the ground pad should be square as well?? I actually don’t know how to change. I transferred the circuit to Ultiboard using Multisim and the pad by default came like that.
also what should ideally be size of pad considering I am not good at soldering…
I haven’t used Ultiboard, so I don’t know how to fix it. You have a ground plane with round holes in it. Inside the round hole, you have a square pad, and it looks like the corners of the square pads are actually touching the ground plane. You either need to change the holes in the ground plane to be square or make them larger diameter so the square pads fit without touching. See if the manual discusses “stackup” or “padstack”. Changing the holes to square is the preferred solution.
The issue with C5 is that you are using the footprint for a polarized capacitor on the board (the silkscreen has a + sign). If you would install a polarized capacitor there (ie, an aluminum electrolytic or tantalum) according to the polarity on the silkscreen, it could explode or catch on fire. Since you are using ceramic caps, they are not polarized, so there’s no safety issue. If you respin the board, you should change the footprint to a more appropriate one to avoid confusion in the future.
n1ist:
I haven’t used Ultiboard, so I don’t know how to fix it. You have a ground plane with round holes in it. Inside the round hole, you have a square pad, and it looks like the corners of the square pads are actually touching the ground plane. You either need to change the holes in the ground plane to be square or make them larger diameter so the square pads fit without touching. See if the manual discusses “stackup” or “padstack”. Changing the holes to square is the preferred solution.
The issue with C5 is that you are using the footprint for a polarized capacitor on the board (the silkscreen has a + sign). If you would install a polarized capacitor there (ie, an aluminum electrolytic or tantalum) according to the polarity on the silkscreen, it could explode or catch on fire. Since you are using ceramic caps, they are not polarized, so there’s no safety issue. If you respin the board, you should change the footprint to a more appropriate one to avoid confusion in the future.
/mike
Thanks again, it seems to be a problem indeed. I will check the manual to solve the problem.
So, to the cases where the square pad is overlapping with ground pour, the components are supposed to be sorted, no???
I could not find any option in ultiboard about changing the circular antipad to square. But in the power plane properties I could change clearance of antipad to pad. So I did that. now they are not overlapping with square pad but they are overlapping each other…do you think that’s a problem???