Question about CMOSH-4E ?

I am just a university students learning electronic technology. I don’t understand some problems . The book said that

CMOSH-4E connect S pole of complementer to the D pole of T1. The datasheet is http://www.kynix.com/Detail/975240/CMOSH-4E.html.

Question 1: When the input is high electrical level, T3, T4 cut-off. T1 conducts and T2’s grid is high level. But the source voltage is unknown. How do you determine the state of T2 ?

Teaching material directly says T2 conduction. I don’t quite understand.I feelthat I should look at the voltage of T1 (DS). But the voltage is not clear.

I want to ask in general how much is it?

http://bbs.elecfans.com/data/attachment … 4uyqzg.jpg

Question 2: A =1 B = 0 , will T2 tube be conducting? Because Ti is off, how to analyze T2 at this time ?

Regards.

Sorry, that datasheet link is no good. It points to some kind of IC with Schottky diodes. And that page doesn’t even provide a datasheet directly. That image looks more like a logic (NAND) gate made up of mosfets. (cmos)

EDIT: Could “CMOSH-4E” mean the image indentifier in the book? Instead of a part number description.

I wonder if there is some translation going of from what is written in the book. Was that book written in english? Anyway, I’ll try to dissect what you have written and try to correct as far as I understand. Hoping we can bridge the confusion this way.

Sidenote: Don’t trust your college books for truth. Writers and editors often make mistakes that live on after print. Always check if the publisher has an errata list with corrections.

Kimmy:
…The book said that

CMOSH-4E connect S pole of complementer to the D pole of T1.

I’m having trouble with the meaning of “complementer” in that sentence. In the image the drain (d-pole) of T1 (the transistor at the bottom) is connected to the (S-pole) of T2 (transistor above T1). ([EDIT]I seem to contradict myself with my later disections. But the following remains true, I think)

If this is supposed to be a CMOS circuit (which it certainly looks like it is) then C in CMOS means “complementary”. In CMOS technology a N-type mosfet is complemented by a P-type mosfet. As T1 and T2 in that image are both N-type mosfets I cannot make sense out of the part “connect S pole of complementer” in that sentence. T2 is not the complementary part of T1. The complementary transistor to T1 is the P-type transistor that has the same input on it’s gate. So that would be T4. Likewise T3 complements to T2.

Question 1: When the input is high electrical level, T3, T4 cut-off.

There are 2 inputs, so it is important to be specific which input is high. A or B, or both. Only an inverter or NOT-gate has a single input. In this case it probably means “when A or B is high, T3 and T4 cut-off correspondingly by their gate state.”

T1 conducts and T2’s grid is high level.

What is “grid”. Could that have the same meaning as “substrate”? I cannot translate that word to either mean drain or source or gate.

But the source voltage is unknown. How do you determine the state of T2 ?

Are both sources of T1 and T2 not connected together, to ground?

Teaching material directly says T2 conduction. I don’t quite understand.I feelthat I should look at the voltage of T1 (DS). But the voltage is not clear.

I want to ask in general how much is it?

T2 only conducts if A is high. I don’t know if that condition is implied.

Question 2: A =1 B = 0 , will T2 tube be conducting? Because Ti is off, how to analyze T2 at this time ?

“tube” means “channel”, right. Answer, see above.

But I might incorrectly interpret the 2 connection lines between T1 and T2. So anybody may correct me if needed.