reset run_and_halt vs soft_reset_halt

Development Boards MicroMod
1

Hi,

I am using GDB/openOCD with OKI ARM7TDMI.

I want to reset target in order to debug from main(). The following GDB command sequence works for me :

monitor reset run_and_halt

monitor soft_reset_halt

b main

c

Since it works, I am basically happy, but I would like to understand exactly what the two first commands (“reset run_and_halt” + “soft_reset_halt”) do. What is the difference between them, do I need both of them, and why ?

I am sure this must be documented somewhere, I just don’t know where.

Thanks,

Anders

2

reset run_and_halt will hardware reset the core and stop the core after the set run_and_halt_time time.

soft_reset_halt was added for arm core that cannot set a breakpoint at the reset vector, eg. some lpc’s and str7 devices.

It is a software reset, eg. set pc to 0 set supervisor mode etc.

Devices such as the str9 can use the reset_halt command because the SRST and TRST are not tied internally on the core.

Regards

Spen

3

Thank you very much, but I have a couple of follow up questions.

Are you saying that “run_and_halt” will halt the CPU after some specified amount of time/cycles ? If so, how do I set the “run_and_halt_time”, and could I set it to 0 ?

In a config file, I see something like :

target arm7tdmi little run_and_halt 0 armtdmi-s_r4

What does “run_and_halt 0” mean here ? Also, what does armtdmi-s_r4 do ?

Is there anywhere I could find important details like this without having to bother you guys with my questions ?

Thanks,

Anders

4

Are you saying that “run_and_halt” will halt the CPU after some specified amount of time/cycles? If so, how do I set the “run_and_halt_time”, and could I set it to 0 ?

Yes. The target is halted after the time specified by "run_and_halt_time ". In theory you could set that time to 0, but that value is just a minimum. The actual time that elapses between releasing the reset and programming the debug request is always going to be greater than this. Even if the JTAG operations to assert the debug request would start immediately after reset went high, there'd be a delay of >50 TCK cycles.

target arm7tdmi little run_and_halt 0 armtdmi-s_r4

This defines a target of type "arm7tdmi" that is little-endian, specifies the reset policy "run_and_halt", tells the OpenOCD that this target is the first device (0) in the JTAG scan chain, and that the arm7tdmi variant is "arm7tdmi-s_r4". The variant has currently no effect, but is there for future use.

Is there anywhere I could find important details like this without having to bother you guys with my questions?

Most configuration commands are documented in the OpenOCD Wiki: [http://openfacts.berlios.de/index-en.ph ... p_Debugger](http://openfacts.berlios.de/index-en.phtml?title=Open_On-Chip_Debugger)

If there’s something missing feel free to ask. It would be great if you could fill in missing parts after you’ve receieved an answer here.

Regards,

Dominic