S3C2413 and OpenOCD

Development Boards MicroMod
1

Hello,

I am trying to use openocd to access my s3c2413 board. I am using a chamelon on which I have uploaded the correct configuration made available for me by amontec.

Here is the configuration I have for openocd

#daemon configuration
telnet_port 4444
gdb_port 3333

#interface
interface parport
parport_port 0
parport_cable wiggler
jtag_speed 1

#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst

#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag_device 4 0x1 0xf 0xe

jtag_nsrst_delay 100 
jtag_ntrst_delay 100 

#target configuration
daemon_startup reset
#target <type> <endianess> <reset mode>
# target arm9ejs little run_and_halt 0 arm926ejs
target arm926ejs little run_and_halt 0 arm926ejs 
# run_and_halt_time 0 500

When I run openocd I get this:

msn@lundi:~/pad/tools/openocdconfig$ sudo openocd -d 3 -f s3c2413.cfg
Info:    openocd.c:84 main(): Open On-Chip Debugger (2007-01-31 12:00 CET)
Debug:   arm926ejs.c:663 arm926ejs_target_command(): chain_pos: 0, variant: arm926ejs
Debug:   jtag.c:1329 jtag_init():
Debug:   parport.c:328 parport_init(): opening /dev/parport0...
Debug:   parport.c:340 parport_init(): ...open
Debug:   parport.c:212 parport_reset(): trst: 0, srst: 0
Debug:   jtag.c:278 jtag_call_event_callbacks(): jtag event: TRST asserted
Debug:   jtag.c:1126 jtag_reset_callback():
Debug:   bitbang.c:223 bitbang_execute_queue(): statemove end in 0
Debug:   jtag.c:278 jtag_call_event_callbacks(): jtag event: TRST asserted
Debug:   jtag.c:1126 jtag_reset_callback():
Debug:   bitbang.c:237 bitbang_execute_queue(): scan end in 0
Debug:   jtag.c:996 jtag_build_buffer(): fields[0].out_value: 0x92063510000000ff
Debug:   jtag.c:1027 jtag_read_buffer(): fields[0].in_value: 0xffffffffffffffff
Error:   jtag.c:1181 jtag_examine_chain(): JTAG communication failure, check connection, JTAG interface, target power etc.

Any clue ?

I have some doubts of how to set OM[4:0].

OM4 takes the XtiPLL or extclk

OM3:0 are for flash setup

Another question. Where can I fond how to setup my config file fo a NAND flash k9F1208

Thanks for your help[/code]

2

Which chameleon configuration did you use (i.e. which one do you believe is the ‘correct’ one)? The wiggler setting from the Amontec configuration utility requires the “old_amt_wiggler” configuration option, as it’s got a non-standard assignment of reset lines.

The wiggler configuration available from Amontec’s website should behave like a real wiggler.

You should use the JTAG Accelerator configuration because it offers the best performance unless you have other reasons to stick with the wiggler setting.

NAND flash isn’t currently supported by the OpenOCD. A patch that adds support for the S3C2410A and the Samsung K9F1208 has been posted to the OpenOCD development mailinglist, but I don’t plan to integrate this as it is, as the “flash” interface in the OpenOCD isn’t really suited for NAND flashes. You could try that patch and see if it works for you.

I’m working on a new “nand” interface and a driver for the LPC3180 NAND controllers which could be easily enhanced to support the S3C2413 (do all S3C24xx have the same NAND controller?), too, but this isn’t finished yet.

Regards,

Dominic

3

Amontec made a “special” configuration file for the Chameleon to suit Samsung’s tech note (sjf2413.pdf in the 2413JTAG_Flash_SJF.zip file in samsung’s web site.

4

sjf241x is Samsung’s (NAND) flash writing utility that bit-bangs the parallel port to control the S3C’s boundary scan chain to toggle the data/address and control lines.

When using the OpenOCD, you need either a “real” Wiggler configuration (chm_appl_jtag_wiggler.amtsvf from http://www.amontec.com/download.shtml) or the JTAG Accelerator configuration (amontec_jtag_accelerator.amtsvf from http://www.amontec.com/jtag_accelerator.shtml).

Regards,

Dominic

5

Dominic:
I’m working on a new “nand” interface and a driver for the LPC3180 NAND controllers which could be easily enhanced to support the S3C2413 (do all S3C24xx have the same NAND controller?), too, but this isn’t finished yet.

Unfortunately some of of the S3C24xx devices have different NAND controllers. For example the NAND controller in the S3C2410A has 6 registers, and the S3C2413 has 17 registers, but the S3C2412/3 seem to have the same interface.

Creating a shared nand interface sounds like a very good idea.

6

Hello Robert,

I’m really sorry. I always meant to reply to you (Robert wrote the NAND patch I mentioned, and posted to the mailinglist, but I failed to reply until now), but I just wanted to get “that last thing” done in my NAND code before writing that mail - well, the NAND code is still not fully done, but mostly working by now, and should be ready for /trunk soon.

Thanks for the contribution you made so far, maybe you want to adapt it to my new NAND interface when it’s done, otherwise I could try to integrate your code in the new framework.

Best regards,

Dominic

7

Dominic:
maybe you want to adapt it to my new NAND interface when it’s done

Sounds like a good plan.