Hi all,
This is something we’re thinking about building here at SparkFun and wanted to gauge customer reaction.
The idea is a SDRAM + CPLD combo on a DIP header board, so it acts like plain SRAM - this way, you could fairly easily add a LOT [128MB] of temp ram to your project without the hassle of dealing with SDRAM.
Would this be something people are interested in?
Cheers,
–David Carne
If you could also clock data into it via SPI (pref) or I2C, that’d be fab!
-marc
Definitely doable.
Cheers,
–David Carne
Are you thinking a board with a DIMM/SODIMM socket on it so users add their own capacity? Would make sense from my point of view…
And given the insane bandwidth and low latency of the latest DDR DIMMs, I’d have to say this really is a good alternative to SRAM!
-marc
I was planning to make it just an SDRAM IC + a CPLD. A full DDR dimm would require an FPGA + a whole bunch of power supply bits - this way I can design it to fit in a dip-ish package.
Cheers,
–David Carne
Not sure what CPLD you are thinking about using and its associated capacity but including a VGA driver would be a nice touch. Think about the possibilities of having a microcontroller friendly interface to a huge chunk of ram with a certain amount mapped to the VGA controller. The controller would only use a small portion of logic and and I/O pins would vary depending on the color depth you want. 5 pins is all you need for basic 8 color support or 8 pins for 64 colors (assuming you don’t want to use a DAC).
Lots of hobbiest don’t understand how CPLDs and FPGAs are used so this may help spark some interest in the topic.
-Bill
“SDRAM + CPLD combo on a DIP header board, so it acts like plain SRAM”
great, go ahead! when will it be available and what is the expected price?
and there is one suggestion from my side. how about two boards, one with 64MB of SDRAM and one with 128MB of SDRAM
Eh, to be honest - it’d be cheaper to just build one model - only one PCB layout and we can buy the 128MB sdram in 2x the qty - and all the chips are close in pricing anyhow.
I can’t give you any pricing info right now, nor a release date as a) I don’t do pricing, and b) I dunno when I’ll design it. Question is if theres enough demand - doesn’t look like too many people are interested, so it might not happen.
Cheers,
–David Carne
Hello David,
if the people are not interested, please can you create the
schematic and CPLD source for how the product would look like?
Regards,
Michael
Remember, it’s the holidays, not everyone comes by!
I’d definitely be interested. I’ve been looking at something like this to tie into a future SRAM alternate. It’d be great to slap this board onto a header feeding an ARM7TDMI external bus interface or similar and get 16MB of RAM (x8 or x16 bus). I was looking at this for a TI ARM chip, actually.
I was actually looking at this (as were you!) for the camera project. You need enough spare logic and pins to allow it to be reprogrammed to act as a pseudo FIFO. I don’t know how much horsepower would be required to allow it to be a true FIFO instead of just a “capture FIFO”. Take a look at the Averlogic FIFO datasheets for a nice way to set up this, but it’d need an SPI interface to allow for read and write pointer selection.
(Addendum)
Video is an interesting option.
As for the video board addition, I’d prefer to keep the video components offboard, as this would allow different video parts to be used per user preferences and some CPLD modification to support as needed. If you DO go onboard, you’d need to have a variant that doesn’t populate the pads to reduce costs for those of us who don’t want to go that route.
It’s also high enough frequency that it may have cause noise issues with the SDRAM. This would be a MAJOR concern with SDRAM clock speed, you’d want to isolate the board sections as much as possible.
Well although it doesn’t look as though many people were interested can i just add my name to the short list of people who are / were ?
The bare bones of the idea were the most appealing to me as i could see it easily developed into a low cost yet large capacity EPROM emulator, something that i have tried and failed miserably to find on the net.
MrS
SDRAM + FPGA + VGA + I2C, now that has possiblities.
I could use something like this to store and retrieve ADC samples (~250k SPS) via SPI.
Hmm. All good ideas - I dunno about the feasibility of having all those different bus interfaces, just in terms of design time. I could design the hardware + firmware for vga controller / basic behavior, but that should be extensible through some verilog work… [Plenty of FPGA pins to pinout, so no issue about adding the interfaces hardware wise].
Cheers,
–David Carne
While I don’t have a project going right now that could use something like this, I can see where it would be very useful. One additional feature would be a way to battery back-up the memory while powering down the rest of the system (and anything that could reduce power consumption would be good). I’d think even 30 minutes would be sufficient for the majority of situations.
I’ve been thinking of a couple of projects that need a large amount of temporary storage. My current thought is to use a flash card but I’m not sure I want it to be removable. Also, I’m not wild about the life expectancy of flash and would have to put some work into distributing the writes over the device. I expect to be gathering a large amount of data.
My company would be interested in an easily addressable / accessible SRAM. I would suggest that you offer just the programmed FPGA and memory chip for those who want to incorporate it in their own product. Sure I could do write my own VHDL and everything, but for a low volume product it’s better to pay sparkfun $5 for something that is tested. But we wouldn’t find a big DIP package particularly attractive.
Hi - FPGA’s actually can’t be “programmed” - or at least not the ones I’m familiar with; they need an external configuration prom to boot from.
It definitely would be more than $5 - the cost of the SDRAM + FPGA in low quantities is much more than that.
Cheers,
–David Carne
To build on my earlier post, my immediate need is for a simple way to take ADC data at about 250Khz sample rate, and store it off to RAM as simply as possible. SPI or I2C works equally well for me. After sampling, the processor would access the data processing. I need quick capture and store, processing is not time critical. I’m not convinced that I can do this well enough using flash (speed and limit on the number of times I can write to the flash). Philba’s suggestion of backing up the processor is another good application for this type of product. Any video aspects would not be a big selling point to me, and I hope that it wouldn’t add significantly to the cost.
I will be following this discussion, and hopefully, I can save myself some effort of rolling my own solution!
Until this board actually does get produced, an alternative that I am using in my thesis project is FIFOs from IDT. They best used when put in a parallel bus (i.e., your ADC has parallel outs opposed to SPI or I2C). The only thing that sucks about these chips is that they are rather pricey. The tradeoff is that they are very, very fast, though.
brennen:
…an alternative that I am using in my thesis project is FIFOs from IDT. They best used when put in a parallel bus (i.e., your ADC has parallel outs opposed to SPI or I2C).
Thanks for the tip. Parallel isn’t a deal killer, it only slightly limits my choices in ADC, although high speed serial would be my choice. A big factor is memory capacity. I’d need somewhere between 32-64mb (by 16 bits) at least. It doesn’t look like IDT has anything that big unless the devices can be daisy chained (I haven’t checked the data sheets yet).