STR912 PLL (off topic)

Development Boards MicroMod
1

Hi people,

I’ve been battling a bit with my ST STR912. I can get it running with the PLL set to 60mHz, but the chip crashes with the PLL set to 96mHz.

Does this sound like a bad chip? I can’t think of any reason external to the chip that would cause it not to run at 96mHz, but fine at 60mHz. (I’ve had the chip replaced with the latest revision number of the chip that ST supplies, since the original silicon on the dev kit had a number of errata issues)

What is making the debug process harder, is that I can’t step my code up to the point where I execute the instruction that causes it to crash.

I follow the following steps to program:

  1. Build program on GCC 4.3.1

  2. Connect openOCD server to the board via parallel port wiggler

  3. Run telnet script to command openOCD to program the flash.

3.1) Issue “reset halt” as the last step in my script, to reboot the chip, but to attempt to halt it, so as not to execute my code yet.

  1. Launch debugger in Eclipse (gdb->OpenOcd->PP wiggler->JTAG)

This all works fine (singe stepping, watching variables, etc) when the 60mHz version of the program is downloaded.

When the 96mHz version is downloaded, the chip immediately crashes after the “reset halt”. The nett effect is that I can’t even start to single step the program to see where exactly the problem occurs in the code.

It almost seems asof the program is already executing before the JTAG command can suspend the chip. In that brief moment the chip crashes, rendering the JTAG incapable.

Would someone give me a quick overview of where the JTAG fits into the execution chain?

Any feedback shall be much appreciated.

Regards,

Frikkie Thirion

2

Good day,

The following solution works on the ST STR912FAW44x6:

Full speed execution of the PLL and internal flash (96mHz)

:lol:

Steps:

  1. Configure the underlying flash configuration into the FMI

  2. Configure the FMI for a bus speed of greater than 66mHz

Note: This will crash the chip if (1) wasn’t performed

Note: This procedure is defined in the ST Flash Programming Manual,

without any reference to the register or procedure in the

Programming Reference Guide! :x

  1. Configure the PLL & clock divider parameters

  2. Enable the PLL

  3. Set the master clock to the PLL

Note: This will crash the chip if (2) wasn’t performed

  1. Toggle LEDs on GPIO7 to compare the speed of different

clock configurations (measured with an oscilloscope).

Test application snippets:

(The ST firmware library was used for the function calls)

// Inform the ARM9 chip about its FLASH configuration

// Boot bank: 512k, Non boot bank: 32k @ 0x80000

FMI_BankRemapConfig(0x04, 0x02, 0x0, 0x80000);

// Set the FMI to run at >66mHz to match the intended 96mHz PLL

FMI_Config(FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_0,

FMI_PWD_ENABLE, FMI_LVD_ENABLE, FMI_FREQ_HIGH);

//This crashes if “Bank Remap config” wasn’t performed

// Setup the PLL parameters

sPLLConf.PLL_EN=TRUE; //M20,N80 ,P3=25mHz

sPLLConf.PLL_MDIV=25; //M25,N192,P3=48mHz

sPLLConf.PLL_NDIV=192; //M25,N192,P2=96mHz

sPLLConf.PLL_PDIV=2;

// Assumption: External oscillator of 25mHz

// Apply clock dividers

// Setup R Clock divider

// RClk = fMaster (96mHz): R clock divider

// (See STR912 Reference Manual, page 63, figure 21)

SCU_RCLKDivisorConfig(SCU_RCLK_Div1);

// Setup FMI clock

// FMIClk = fRClk (96mHz)

SCU_FMICLKDivisorConfig(SCU_FMICLK_Div1);

// PLL program procedure, according to the STR912 Reference Manual,

// page 65, paragraph 2.4.10:

SCU_PLLFactorsConfig(sPLLConf.PLL_NDIV,

sPLLConf.PLL_MDIV,

sPLLConf.PLL_PDIV);

eErrorStatus = SCU_PLLCmd(ENABLE);

//Setup master CPU clock

eErrorStatus = SCU_MCLKSourceConfig(uwClockSource);

//This crashes if PLL freq > 66mHz and FlashConfig:Freq_High wasn’t set

cJ=0;

while(1)

{

cJ++;

GPIO7->DR[0x3FC]= cJ;

}

Results:

PLL=48mHz, RClkc=48mHz, FMI=48mHz => 1.066mHz

PLL=96mHz, RClkc=96mHz, FMI=48mHz => 1.8mHz

(Assumption: Prefetch is responsible for the faster than expected

execution time

)

PLL=96mHz, RClkc=96mHz, FMI=96mHz => 2.01mHz

(Great Success)