Trouble halting and loading code for an LPC2138

Development Boards MicroMod
1

I’ve been trying to get OpenOCD to halt an LPC2138 via the telnet interface and load my code but I’m getting conflicting information. For example executing halt never actually results in a halt but reset halt does. But when I poll afterwards or load code then OpenOCD tells me I’m still running. In any case I don’t actually think my code is being loaded because I can’t get it running. Below is my session in telnet all the messages from openocd and my config file.

Thanks,

gatechman

telnet session

phillip@phillip-laptop:~/RoboJackets/RoboCup/firmware/robot$ telnet localhost 4444
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> halt
requesting target halt...
> reset halt
> Target 0 halted
target halted in Thumb state due to debug request, current mode: System
cpsr: 0xffffffff pc: 0xffffffef
> halt
requesting target halt...
target already halted
> poll
target state: running
> flash write_binary 0x0 /home/phillip/RoboJackets/RoboCup/firmware/robot/robot0.bin 0x0
failed writing file /home/phillip/RoboJackets/RoboCup/firmware/robot/robot0.bin to flash bank 0 at offset 0x00000000
can't work with this flash while target is running
wrote  2616 byte from file /home/phillip/RoboJackets/RoboCup/firmware/robot/robot0.bin to flash bank 0 at offset 0x00000000 in 0s 211us (12107.523697 kb/s)
> halt
requesting target halt...
> reset halt
> Target 0 halted
target halted in Thumb state due to debug request, current mode: System
cpsr: 0xffffffff pc: 0xffffffef
> reset run

openocd messages

Info:    openocd.c:93 main(): Open On-Chip Debugger 1.0 (2008-01-18-12:07) svn:259
Info:    openocd.c:94 main(): $URL: svn://svn.berlios.de/openocd/trunk/src/openocd.c $
Error:   jtag.c:1251 jtag_examine_chain(): JTAG communication failure, check connection, JTAG interface, target power etc.
Error:   jtag.c:1440 jtag_init(): trying to validate configured JTAG chain anyway...
Error:   embeddedice.c:181 embeddedice_build_reg_cache(): unknown EmbeddedICE version (comms ctrl: 0x00000000)
Warning: arm7_9_common.c:755 arm7_9_assert_reset(): srst resets test logic, too
Info:    server.c:67 add_connection(): accepted 'telnet' connection from 0
Warning: arm7_9_common.c:766 arm7_9_assert_reset(): srst resets test logic, too
Error:   arm7_9_common.c:967 arm7_9_halt(): can't request a halt while in reset if nSRST pulls nTRST
Warning: arm7_9_common.c:954 arm7_9_halt(): target was already halted
Warning: arm7_9_common.c:766 arm7_9_assert_reset(): srst resets test logic, too
Error:   arm7_9_common.c:967 arm7_9_halt(): can't request a halt while in reset if nSRST pulls nTRST
Warning: arm7_9_common.c:755 arm7_9_assert_reset(): srst resets test logic, too

my config file

#daemon configuration
telnet_port 4444
gdb_port 3333

#interface
interface ft2232
ft2232_layout jtagkey
ft2232_vid_pid 0x0403 0x6010
#ft2232 device desc
jtag_speed 0
 
  
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst

 
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag_device 4 0x1 0xf 0xe

 
#target configuration
daemon_startup reset

 
#target <type> <startup mode>
#target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
target arm7tdmi little reset_run 0 arm7tdmi-s_r4
run_and_halt_time 0 30

 
working_area 0 0x40000000 0x40000 nobackup

 
#flash bank <driver> <base> <size> <chip_width> <bus_width> <target#> <variant> <clock> ['calc_checksum']
#the chip_width and bus_width fields don't need to be set for LPC2000 devices
#The size needs to be set to the user-accesible size for lpc2138 and lpc2148 ie it must be 0x7d000 (500kb)
#instead of 0x80000 (512kb)
#see openocd quick-cmd card for more info
flash bank lpc2000 0x0 0x7d000 0 0 lpc2000_v2 0 14740 calc_checksum
flash bank cfi 0x80000000 0x400000 2 2 0

[/code]

2

The very first message you get from OpenOCD after it’s startup message is:

Error: jtag.c:1251 jtag_examine_chain(): JTAG communication failure, check connection, JTAG interface, target power etc.

Until you fix that, the other messages are pretty much meaningless because they all depend on communication between OpenOCD and the ARM TAP controller. Unfortunately, JTAG communication failure can occur anywhere between OpenOCD and the TAP controller, so it could be caused by your PC, your cables, your JTAG pod, or on your target board. You need to be sure that JTAG is enabled on your target chip, that the target chip is actually clocked and running, and that you are actually getting all the JTAG signals to the board. Your config file shows that you are using the highest possible JTAG clock frequency, so you also need to be certain that your setup can actually support that high a clock frequency. When I have run into this sort of problem myself, one of my first steps is to slow the JTAG clock, at least temporarily, to see if that is the reason for the communication failure.

Since there is no one single cause for JTAG communication failure, it is really difficult to offer any specific advice. However, there is no need to worry about your other warnings and messages until you actually have JTAG communication between OpenOCD and your target.

–Dave