I'm pretty sure this is directed at me. I have no idea what you're trying to say though.Philba:
hmmm, lots of rocks out there then. you can find plenty of examples, though. guess they all fail.
I like to make my PCBs look pretty, and stick to 45degNleahciM:
The right angle traces issue is mostly a cosmetic thing. But the diff pair is not and needs to be rectified.
angled corners and do a DRC for grid placement.
I’m convinced that the effort to do it right the first time
has stopped me from joining the “green coaster” club.
I know from reverse engineering other products that
some very non-pretty PCBs make it to production and
seem to work.
The issue about the “diff pair is not and needs to be rectified”
is probably one of those cases. If I was asked to prove it one
way or the other I’d expect to use some fancy test gear
that I don’t have on hand (TDR, network analyzer).
I can’t think of one case for PCB that wasn’t RF or
wideband analog video circuit that needed a PCB layout
spin to meet spec. Then again, I’m not currently
designing DDR memory or other high clock speed
digital PCBs either.
Bottom line, don’t sweat the diff pair issue if the PCB
traces are less than a quarter wavelength. (About two
feet for USB data lines, Half that for IEEE1394/firewire).
Anyone else been caught up in diff pair PCB designs that
did make a measureable different to the outcome?
Phil, Check your PMs over at NandV.Philba:
hmmm, lots of rocks out there then. you can find plenty of examples, though. guess they all fail.
We now return to our regular programming.
bigglez:
I can’t think of one case for PCB that wasn’t RF orwideband analog video circuit that needed a PCB layout
spin to meet spec. Then again, I’m not currently
designing DDR memory or other high clock speed
digital PCBs either.
Anyone else been caught up in diff pair PCB designs that
did make a measureable different to the outcome?
I’ve never had a failure in this regard either. I have messed up a 2.4GHz balun before (which without the right test equipment is basically impossible to diagnose).
Just a quick note. While I do agree that you’d really want to keep the USB data lines as straight as possible and as close to the required impedance as possible, I think the biggest problem is likely to be that your USBDM line is roughly twice as long as your USBDP line.
There is no such thing as a “slow” full-speed USB device. It will switch at 12MHz regardless of your data rate, and the USB spec doesn’t allow for much error in the timings.
The FTDI notes, available at http://www.ftdichip.com/Support/Knowled … index.html point out the trace-length issue.
EDIT: in all likeliness, it’ll still work, this is just generally useful stuff to keep in mind. It’s amazing what you’ll get away with, but you can never count on it 100% if you don’t do it right.
The FTDI notes, available at http://www.ftdichip.com/Support/Knowled … index.html point out the trace-length issue.
Awesome! Thanks for the pointer. I can’t believe I never thought to check more than their datasheets. 
Appnotes are indeed a goldmine
Twelve megahertz is a wavelength of about 25mmkissin:
There is no such thing as a “slow” full-speed USB device. It will switch at 12MHz regardless of your data rate, and the USB spec doesn’t allow for much error in the timings.
(82ft). Even if the waveform rise and fall times
were 2ns each, thats 500MHz, or a wavelength
of 600mm (two feet).
How big is this PCB?
Yeah, bigglez, and if it was running on sinusoidal waves, you’d be spot on. But it’s running on square waves. Remember Fourier series expansions? Infinite odd harmonics? That’s the one.
Anyway, like I said, it’s just something to keep in mind, especially since the FTDI appnotes call it out specifically.
Also as I said, It’ll most likely work just fine, but the OP asked for feedback, and it is something to be aware of. Why lay the board out incorrectly if you have the option of doing it the Right Way? Even just for the sake of being a perfectionist.
EDIT: spelling
EDIT the second: the USB spec also demands that there is a maximum skew on the differential pair of 100ps (section 7.1.3). If we assume that the signals propagate at C (which you have, and which is not accurate) then this gives you 30mm to play with. Not far.
USB cables have a velocity of propagation of no slower than 5.2ns/m. Which is about half that of the speed of light. If we assume that you manage to match this speed with your PCB design you’re down to about 19mm difference in trace lengths. Even less.
We're now splitting hairs and not helping the OP.mkissin:
if it was running on sinusoidal waves, you’d be spot on. But it’s running on square waves.
The 2ns rise and fall times is for the USB square-wave
data at a 12 MHz clock rate, sorry if that wasn’t clear.
FR-4 propogation is about 0.6*C. IMHO, 100ps skew
is not a very practical spec limit for a cable bundle…
Regardless, that’s the spec. If you violate it, you’d need to be prepared for failures.
I’d also argue that this is indeed helping the OP, as his design is very close, if not over, the excess trace length limit.
mkissin:
Regardless, that’s the spec. If you violate it, you’d need to be prepared for failures.
I wouldn’t know how to measure that spec, nor do I
have access to equipment I presume would be
required to do so.
mkissin:
I’d also argue that this is indeed helping the OP, as his design is very close, if not over, the excess trace length limit.
So why not construct two prototypes, one with and
one without the critical lead/trace/conductor limits?
Perhaps both will work, perhaps not? I couldn’t say.
That’s the thing. You don’t need to measure it. If you follow FTDI’s appnote and make the two traces the same length, you’re safe. There’s really no need to make two prototypes either. Why bother making one that unnecessarily pushes the limits when it’s so easy to simply do it right?
Both might well work. In fact, they almost certainly will, as the chip designers probably built their chips such that they aren’t butting up against the limits of the spec. But why push it? Don’t poke the sleeping bear if you don’t have to.
As a general rule, lay your components out such that the critical traces are going to be easy to route correctly, and then route those traces first. Preferably by hand if you plan to use an autorouter that lacks smarts, or you’re unsure how to set it up to specify critical traces. Then lay out non-critical traces such as power supplies last.
The best bit is, that technique will give you a good shot at a working layout for switch-mode power supplies, sensitive analogue circuits or high-speed comms circuits, and everything else.
I don’t know how you do things, but typically it’s a good idea to figure out what parts of your circuits are important. Appnotes will often give you either a hint or the straight-out answer, such as in this case. You then know where to take care.