I breadboarded a USB design using a Microchip 18F4550. It worked perfectly well on the breadboard, then I created a prototype with BatchPCB. The design uses a 20MHz crystal with 15pF load capacitors.
My PCB is almost completely SMT, as opposed to the breadboard. However, I think I flubbed the layout, because the board works with the internal oscillator, but won’t operate at 20MHz. I suspect that my traces should have been equal length instead of completely asymmetrical as they are, but I don’t know enough about PCB layouts to confirm this.
I don’t have the Eagle files with me right now, but at the risk of total public humiliation and the hope of getting some help, I’m posting the layout pic from BatchPCB.
Is there a good source with tips like the below for beginners on routing SMT boards? I just found the below in the forum, which was very helpful.
inventore123:
Eagle’s autorouter does not suck, it must be used properly. For example, you route manually all critical parts of the design, like traces from a crystal to a micro, and temporarily fill the manually routed pieces with some t_restrict, b_restrict to avoid the autorouter placing high speed digital lines close to the crystal. Or things like the ground lines of a DC-DC converter to avoid poor gnd design and high ripple, all things that an autorouter cannot know. Then you start the autorouter, that is enough intelligent not to ripup the manually routed traces. To avoid long lines with many vias you can reduce grid size, increase ripup level, and add more optimizations. My projects are extremely simple compared with what you want to do, but I think that eagle autorouter will be a better choice than manually routing everything.
[[link to original post here](http://forum.sparkfun.com/viewtopic.php?t=8313&highlight=crystal)](http://forum.sparkfun.com/viewtopic.php?t=8313&highlight=crystal)](http://img187.imageshack.us/i/20210topsm.png/)](http://russosv.info/w/Projects?action=AttachFile&do=get&target=20210_top_sm.png)
i don’t like the way you went around with the one trace, I usualy try and keep the two traces together in a line from the pins right to the crystal and as close to 1/2 inch or less i can keep it, and i am trying to run ground around all of it
The traces between you processor and the crystal should be as short as possible - your’s are way to long. Microchip has several application notes that address the selction of the crystal, the loading caps and PCB layout; AN588, AN949 & AN1288. I’m sure there are others. You can download these from Microchip’s web site.
Here’s a section from one of the App notes regarding layout:
The oscillator circuit connections should be as short as
reasonably possible. This suggests that the oscillator
circuit should be placed next to the controller and on
the same surface. This also suggests that the loading
capacitor grounds should be connected directly back to
the controller. If possible, there should be no other
connections or vias between the loading capacitors
and the controller ground, except at the controller itself.
The exception would be if a ground plane is present
Thanks GSM Man… I did some searching of the Microchip web site looking for advice, but didnt find those exact App Notes that you referenced. The quote and the ANs you provided are very helpful, thank you.
From AN1288- again, very helpful… thanks!
If the traces to the oscillator are kept short, under 10
mm-long each, their capacitance will be very low and
almost negligible.
I think I'm going to try moving the 0.1uF cap a bit, bringing the crystal closer to the MCU, and then hand-routing the crystal traces so that they are both the same length and much shorter.
The main problem I see is not the length of the tracks from the crystal to the CPU (although they are too long as discussed). It is the ground connection on the load capacitors. Each of these capacitors should have its own via nearby directly to the ground plane. They should not be connected together like this. I also wouldn’t route other connections through the crystal like that.
This is a good grounding rule generally - don’t be afraid to use LOTS of vias to the groundplane, and put them as close as practical to the component pins. Are you using the bottom layer as a groundplane? You should be! Single sided PCBs should almost never be used, especially with high-speed circuits.
I would never bother with an autorouter for such a simple layout - much better just to route everything by hand IMO.
Thanks MichaelN… I did not know that about the capacitors or routing under the crystal… that’s exactly what I was talking about-- how does a beginner hobbyist like myself learn these little layout tips when transitioning from breadboard to PCB?
Are you using the bottom layer as a groundplane?
Yes, the bottom layer is a copper pour used as a ground plane... sorry I did not show it here; there's not much on it except for 1 trace and the ICSP header.
I’d just move the crystal closer (like right next) to the pic and make sure the caps have a good ground in common. Route all the other traces away from the crystal and make sure there is a ground “guard ring” around it.
It looks like your copper plane isn’t connected to anything. Try naming the rectangle GND (or what every you are using for ground). I wonder if those orphan copper pours are causing a problem.
By the way, you should check for solder bridges, shorts, opens and so on. It could be as simple as a bad solder joint.
Russ, I wish I could offer a good book or reference, but I’ve picked up these types of things from lots of sources over the years, as well as by making lots of mistakes. I’m sure there are good books on the topic though.
A few points I keep in mind when designing (2-layer) PCBs:
Carefully place components to minimise overall track lengths. If 2 components have a lot of connections between each other, try to put them close togehter.
Try to separate high-speed digital and sensitive analog parts of the circuit to different parts of the PCB.
Try to dedicate the bottom layer to a ground plane, and minimise any breaks in this plane. Where it is unavoidable to have tracks on the bottom layer, minimise their length.
Avoid having tracks carrying high-speed signals cross over any breaks in the ground plane. This is because the “ground return current” won’t be able to travel directly under the signal track, creating a loop which can cause EMI issues as well as injecting noise into other parts of the circuit.
For all pins connectoed to ground, have a via to the ground plane located as close a practical to the pin.
Locate decoupling capacitors as close as practical to the pins they are decoupling.
Don’t use split groundplanes unless it is really necessary for very sensitive analog circuitry, and then be VERY careful how you implement them (eg no tracks can crosss the split).
One other thing with designing circuits, try to make sure any pins connecting to the “outside world” are well protected against ESD, voltage surges, incorrect polarity etc.
For example, I never directly expose microcontroller pins to a connector without protection. Sometimes this is as simple as adding a resistor (allowing the internal protection diodes in the micro to do their job without being damaged), and sometimes you’ll need to add TVS diodes etc or add additional interface components.
Philba, zarcondeegrissom, MichaelN (and again, everyone else who has responded so far)-- I can’t say thanks enough. You are all so helpful; it’s greatly appreciated. It’s obvious that you all have plenty of experience with this and I’m thankful you are willing to share it.
I ripped up all the signals and re-routed the board by hand. Would you guys mind taking a quick look and seeing if you have any additional comments?
By the way – I wanted to mention that the top copper pour isn’t connected to anything, but the bottom pour is a ground plane. I wasn’t sure whether it was correct or not to (a) make both planes GND, and (b) have a ground plane so close to all my components. I thought it might increase the risk of a short. The top pour is simply a ‘reflex’ from when I was home-etching boards, to make the etch process faster. Please let me know what you think is the best methodology.
Also, is it OK to have the ground pour running underneath the crystal? I hadn’t really thought of this before, but what would happen if I inadvertently shorted one of the crystal’s leads to ground? Couldn’t that mess up the signal too?
I’m planning on putting this design-- and the software that will go with it-- on my web site and releasing it as open source.
Edit: By the way, I tried green-wiring the crystal directly to the OSC1 and OSC2 pins of the MCU, and the MCU ran at 20 MHz consistently each time I’ve started up the board. So I suspect that the 2 uneven, long traces were causing the problem I initially mentioned. I’m having problems now communicating with the FT232RL, but I think that’s probably another issue. I think i have pretty much destroyed my current prototype from over-soldering the components so I may have to rebuild it on the 2nd board I got.
Michael-- your point is well taken with the protection. I think that the only “outside world” connection in this circuit is the ICSP header. I intend to remove this connection once I’ve finished developing the software/firmware as updates will probably be done via a USB bootloader.
Edit 2: Removed the ground layer from under the crystal… do you think this is better? Also moved the via near the crystal a little, and took Michael’s advice re: a separate via for each ground on load caps.
I woud definately connect the top copper pour to ground. Are you worried about shorts because you aren’t getting a soldermask? I always like a soldermask, but if you’re not getting one you could always increase the separation in the design rules.
Bond the top and bottom groundplane together using a bunch of vias, particularly in the area where you have tracks on the bottom layer (to minimise the distance the ground-return currents from those signal lines will have to travel).
It is normally recommended to pour the groundplane underneath the crystal. If you have a soldermask, there shouldn’t be any worries about shorts. The additional capacitance on the crystal pins shouldn’t be an issue.
I don’t normally consider the ICSP / JTAG connectors the “outside world”, since this is not something that is normally accessed by the end-user. Thus, I don’t include additional protection on these lines. I would re-consider this if the ICSP / JTAG lines were actually accessible from the outside of the box during normal operation.
Static electricity can be a big danger for un-packaged electronics, but if you are sensible you should be OK. Once the PCB is packaged in a box, it is normally only susceptible to the lines that are actually presented to the outside of the box. In a production unit, depending on the end application, you might want to include additional protection on the USB data lines. You can’t use normal TVS devices for this (as the capacitance would be too high). Something like the SP0502BAJTG is designed to work on high speed data lines.
Re the 2 separate vias for the crystal load caps, this isn’t really needed in this case (they are touching each other), but it isn’t a problem either. The main thing is that all ground lines have a short connection to the groundplane, and you have acheived that.
Thanks Michael… I revised it according to your comments. I added back the ground plane underneath the crystal, made the top layer VSS, and also added a bunch of vias between the top and bottom layer (did I go overboard?)
There wasn’t a ton of room near the bottom layer tracks to add vias because of the top components, and there is isolation between them which prevents me from adding vias in between. Bottom isolation is 12 mil, and top is 16 mil. Is it better to rearrange the bottom tracks so I can add vias in between them?
I am getting a soldermask… I think that’s included in the BatchPCB process. I’m worried about shorts because I just don’t know any better!
Thanks again, also thanks for the tip on the USB lines, def will add SP0502BAJTGs for ESD protection in the next revision.
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Latest: Added a couple more vias and fixed some artwork
I think that looks ok but if it was my design, I’d move the crystal even closer. Since this is only a 20 mhz design, the way you have it should be fine.
Out of curiosity, why did you position the pic and a lot of the passives at a 45 degree angle? I think it would fit fine without the rotation.
Thinking about your first design, I still think the problem is some sort of short or open. Even though it’s suboptimal, it should at least run.
Thanks Philba… I would have moved the crystal closer, but there is a decoupling cap close to the MCU so I wasn’t sure what to do. I always have read that you should put your decoupling caps as close as possible to the MCU. I realize I could have used a smaller cap, but 1206 is as small as I am willing to go at this time because my soldering skills aren’t that great!
I only put the MCU and passives at a 45 degree angle for fun… I thought it looked kind of cool on some of SparkFun’s designs.
Thinking about your first design, I still think the problem is some sort of short or open. Even though it’s suboptimal, it should at least run.
I’m going to try populating my second copy of the current board I got and see if it works…
if it was my design, I’d move the crystal even closer
So is it more important to have the crystal close to the MCU or the coupling cap close to the MCU? My rationale was that the crystal is outputting a varying signal, so it would probably be more important to have the decoupling cap close to the MCU to minimize noise near the MCU. Really, I have no idea, just guessing… My problem is that the VCC/VSS is right next to OSC1/OSC2 so there is limited physical space.
I think you’ll be fine with things the way you have them. The decoupling cap is pretty close to the power supply pin anyway.
Re component sizes, don’t be afraid of 0805 and even 0603 sizes. I don’t have good eyesight or fine motor skills, but I can still easily manage 0603. I normally use solder paste & a skillet or hot air gun (ie, for paint stripping) to reflow boards.
The right lower pad on “C3” with the two traces going off the pad, round the inside of that sharp “V” a little bit. You don’t want that shape on any trace. If you must come into a square pad from an angle, hit the corner dead on (LED1, R2, 4550-C3, C4-4550 ground trace), or you’ll get an acid trap. If the inside of the “V” is sharper then 90degrees, it’s to sharp. even 90degrees may be pushing it for some fabs.
I read that your dealing without a solder mask, so I understand the “Floating” copper areas between stuff. I’d try to find a way to ground them with more clearance, or remove the free floating tiny antennas/tuning forks. example under the “0.1” label for C3 I think.
“decoupling cap close to the MCU to minimize noise near the MCU.” true. Remembering where dealing without a solder mask to prevent solder bridges, so moving either closer isn’t possible at this point. I would not want to solder that by hand, with my lack of SMT soldering skills. I’d end up killing parts.
Don’t be afraid to make your +V trace thicker, it will reduce the voltage drop at the end of the run. Even if there is only milliamps on the power traces, thicker power traces have less inductance and less resistance, then thin ones. It also helps cool the parts they feed. This doesn’t always apply to signal traces, just power traces.
Is the shell on a USB connector supposed to be grounded for RFI reasons?(I don’t know) To ground loop, or not to ground loop, that is the question… lol That’s up to You.
According to the USB spec. the shell shouldn’t be grounded. I did ground it on a PCB of mine, before I knew any better, but it didn’t cause any problems.
