Hi All,
Does anyone know what the clearance limits are for vias and drills? I’m intending to place vias connecting copper areas in the top and bottom layers for thermal relief, and am wondering how close I can place my vias together.
Actually, it would be great if there was a BatchPCB .dru file we could download and use in our projects… but that’s probably a different topic. 
Back on topic, is it possible to find out what drill sizes are actually used by Gold Phoenix? I’m asking because I work in metric whenever I can, but all the info on BatchPCB is in imperial. I was thinking it’d be useful to customise the drill menu (SET DRILL_MENU) which is used for vias or through hole pads with the actual drill sizes used. The thing is, what happens if I’m working in one system (e.g. metric) and drill bits sized in the other (imperial) are used. Are they rounded up to the next drill size, or is the closest match used?
EDIT: I forgot to mention, there is a difference between via clearances and drill distances as seen by Eagle’s DRC. I guess via clearance looks at the copper ring on the via, and is more critical when two vias of different signals are next to each other, while drill distances only seem to look at the hole. Curiously I tried two vias next to each other connecting the same top and bottom polygons, and I got a via clearance error. I’d have thought that wouldn’t be an issue as the entire area is all copper.