I’m working with a QFN chip with a center pad - also known as an exposed pad (EP). What is the preferred way to connect the pad to a bottom ground plane using a via? Is it ok to just stick the via on top of the pad, rename the via to GND, and call it a day? When I do this and then hit the ratsnest button you can see a small unrouted link between the via and the pad directly beneath it. I should note that the datasheet for the chip does show two vias on top of the pad. Any help would be greatly appreciated.
Thank you Rolf. That does appear to be the correct answer. I actually called Cadsoft to ask them this question and they said it would be fine and to ignore DRC errors and the fact that there is a small unrouted line between the via and the pad beneath it. If you run the auto-router it would create a short trace between the via and the pad that you wouldn’t be able to see without clicking on it.
Not a QFN but this is the same idea done in Eagle for a TSSOP package with a thermal via. The large via in the center is for soldering and the smaller vias are for added heat transfer between layers.
That via layout may not be manufacturable. Thermal vias in central pads are usually really small and lots of them…13-15 mil from what I’ve seen and used. The big via might be OK if you are intending only to solder this by hand.
However, I’m also required to comment on how some of the traces leading to the pins are actually wider than the solder pads, many are skewed at odd angles such that the clearance between traces might be too small to manufacture. Also confused about those traces that run along the inside of the solder pads, connect to the thermal pad, and apparently makes a near-90 degree crossing connection with the trace coming from the top right pad?
While I appreciate the critiques, please note that the screen shot I posted was from a very early stage in the routing of a relatively complicated board. Several years ago (4-5 maybe?) another person was curious how I handled the TSSOP thermal pad on Allegro motor controller ICs so I posted that picture which is what I had available at the time. I never got a screen shot once I was finished but the boards have been going strong since then.
Rest assured, the via layout manufactured just fine on this board. The traces leaving pads at slightly odd angles was a result of the grid being set too coarse. It was touched-up before the board went into production. The trace leaving the top right pin going into the thermal pad was routed before I decided to add a termal pad to the top layer in addition to the bottom layer thermal pad which already existed. It connects to another point within the pour but disappears when you hit ratsnest. Certain traces being wider than the pads was intentional for high-powered signals. This board was manufactured using 0.5 Oz. copper to save money so it was necessary to widen the traces as much as the DRM rules would allow in order to prevent overheating and signal loss.
I figured it was some intermediate layout, don’t worry. I just wanted to make sure it didn’t reinforce any bad habits with our fledgling PCB routers here. And by “manufacturable” I mainly mean that the via layout would probably not be ideal if you had a company assemble the boards in quantity. It might work, but the large via would probably wick out a lot of the solder paste.
