Is it possible to put vias within smd pads or will that violate the sparkfun clearance requirements?
To be more specific, I wanted to use smd power supply bypass capacitors on the solder side of the board and connect them to an opamp on the component side directly above with vias placed inside the capacitors’ pads ([picture).
Thanks for any help.](ImageShack - Best place for all of your image hosting and image sharing needs)
tyre:
Is it possible to put vias within smd pads or will that violate the sparkfun clearance requirements?
I have ordered several boards from SFE and I think all of them had several smt pads with vias in them.
Wouldn’t that just be a through hole pad?
In terms of your gerber files, a pad is no different than a normal trace on your board. The via and pad can touch so long as they are part of the same signal. So long as you do not violate distances between 2 different signals or holes, you should be all set.
As a “for instance”, I just designed a board for work that uses a TSSOP-24 chip with a thermal pad underneith it that is also its primary ground connection. I put a small ground plane under the chip on the top layer and a much larger ground plane for plenty of thermal mass on the bottom layer. I then used vias defined as a “ground” signal and placed them under the thermal pad area. That let me solder the thermal pad down without having the reflow the board since I could do it from the back side. Unfortunately I needed the boards almost next day so I couldn’t use Sparkfun’s service, but it passed my own DRC with much looser tolerances then Sparkfun’s pooling service can provide.
-Bill
That shouldn’t be a problem. There is nothing wrong with putting a via under a chip like that, its done all the time – especially on larger parts. However, I am glad that you included a picture with your description because I got the impression that you wanted a “blind or buried via.” I am doubtful that the manufacturer would be happy about these. These vias are typically underneath a pad or only between certain layers on a multilayer board (obviously doesn’t apply here). Both of which should generally be avoided because if you have ever needed to debug or trace a signal its nearly impossible!
Ooops, I didn’t even notice that you attached a picture. What you have done is OK so long as your clearances are in line with Sparkfun’s guidelines.
Here is a picture of what I was trying to explain in my previous post. The chip in the center is a TSSOP-24 with a thermal pad underneith. You can see the red ground plane directly under it. On the bottom layer (which is not shown) is another larger ground plane which is restricted so no traces can run through it. I then put vias through the two planes directly underneith the chip to aid in soldering and heat transfer. I then drew an area on the t_stop layer to make sure there was no solder mask between the ground plane and the thermal pad on the chip.
