Sounds possible. But the communication with the disk and the ethernet controller will be slow. I wouldnāt aim for more than 10 Mbit ethernet.
And you will probably not be able talk any sophisticated protocol like SMB or NFS that requires you to parse the filesystem and handle multiple connections. There is not enough RAM to do that.
Thereās also SCSI-over-ethernet (possibly several varieties), as well as Sunās ancient ānetwork diskā protocol, MITās āremote virtual diskā protocol, firewire-over-IP ā¦
I think you would definitely want to be able to sustain a minimum for 30-40 Mbit/S through the NIC. Any less than that and you will be pretty unhappy. Given that you can get fairly inexpensive NAS boxes, Iād not sure why you would want to build your own.
If you insist on doing it, Iād look at the AVR32 line. You can run AVRās Linux on it so you get all the protocols you would ever want for āfreeā (free as in beer). Rolling your own is a big undertaking. The AVR32 has DMA so you should be able to run at pretty high speeds.
Youād have to integrate in the disk interface but I know that people are doing that now and there may well be examples to draw from.
if you were expecting to find a chip that you can plug into a solderless breadboard, well, forget it. TQFP 100 is pretty easy make a board for. In addition to the processor, you are going to have to add the ethernet chip and an interface for the disk. Mostly surface mount there too. Unless you have some experience I suggest you either buy a nas box (look here: http://www.newegg.com/Product/ProductLi ā¦ 0Ā±+%24200 ) or get an old PC, install linux, turn on samba and be done with it.
It should be possible to increase the disk<->ethernet bandwidth by making the parts talk directly to each other as it was done in the Atmel article with the SRAM chip. This saves two port accesses per byte. The cpu would just need to toggle the IOR/IOW line.
Could it be possible to drive the IOR/IOW lines with a half 74123 triggered by the DMAREQ line (and retriggered by the other half)?
Then the microcontroller could sleep and wait for the interrupt.
One could as well attach the 25Mhz clock necessary for 100Mbit ethernet to a 74161 counter and reset it at 3. Bit 1 should provide a nice waveform for MDMA 2 transfers.
This timing should be possible with the Davicom DM9000A and the Asix AX88796B.
Well that should work, but the Davicom DM9000A and the Asix AX88796B are smd and you cant get them at like mouser or elsewhere. If get a PCB place to do it it would cost way to much.