Can't mask interrupts during step with OpenOCD and cortex-m3

somers · August 26, 2008, 4:58pm

I’m using openocd to debug an STM32F101C6T6, and I can’t mask interrupts during step. According to the Cortex-m3 reference manual, i should be able to do this by setting bit 3 (C_MASKINTS) of DHCSR (0xe000edf0). I can set that bit from the openocd telnet interface, but as soon as I try to step, i get whisked into an ISR and C_MASKINTS is cleared again. My program has timer-based interrupts so it’s pretty difficult to debug if I can’t mask interrupts during step. Has anybody gotten this to work on a cortext-m3? Any ideas? I’ve tried it with both r737 and r971 of openocd. Here are the commands I’m using to read and set C_MASKINTS:

mdw 0xe000edf0

0xe000edf0: 00030003

mww 0xe000edf0 0xa05f000b

mdw 0xe000edf0

0xe000edf0: 0003000b

target state: halted

target halted due to single-step, current mode: Handler External Interrupt(18)

xPSR: 0x61000022 pc: 0x080007d8

SWJ-DP STICKY ERROR

dcb_dhcsr 0x30007, nvic_shcsr 0x20000, nvic_cfsr 0x0, nvic_bfar 0xe000edf8

SWJ-DP STICKY ERROR

dcb_dhcsr 0x30007, nvic_shcsr 0x20000, nvic_cfsr 0x0, nvic_bfar 0xe000edf8

Block read error address 0xfffffff0, count 0x1

unexpected error -107

mdw 0xe000edf0

0xe000edf0: 00030007

Could the SWJ_DP STICKY ERROR be the culprit? I don’t know what to do about that error and couldn’t find much documentation on it.

CoupeDLX · November 19, 2008, 2:49am

I was encountering a similar problem with my STM32. It would not set C_MASKINTS when single stepping (“s” or “n”) from GDB. I made a change to cortex_m3.c which seems to fix this. There was a check in the “cortex_m3_step” function that explicitly cleared this bit. Why was this done?

My change to ensure it is set before stepping is attached.

$ svn diff target/cortex_m3.c
Index: target/cortex_m3.c
===================================================================
--- target/cortex_m3.c  (revision 1173)
+++ target/cortex_m3.c  (working copy)
@@ -658,9 +658,9 @@
 
        target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 
-       if (cortex_m3->dcb_dhcsr & C_MASKINTS)
-               ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN );
-       ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY| C_STEP | C_DEBUGEN);
+       if (!(cortex_m3->dcb_dhcsr & C_MASKINTS)) // ensure ints are masked when we step
+               ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN );
+       ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
        ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 
        /* registers are now invalid */

somers · November 19, 2008, 11:40pm

Fabulous! That works for me. Have you submitted this patch to the mailing list so the devs will know about it?

ntfreak · November 20, 2008, 11:19am

Hi,

I have looked into this issue and committed a slightly different patch to svn.

latest code in svn as ever.

Cheers

Spen

somers · November 20, 2008, 3:51pm

Masking interrupts during step does not work for me in r1180. When I try to step, the openocd console returns the following error and I trap in an ISR.

Error:  SWJ-DP STICKY ERROR
Error:  dcb_dhcsr 0x30003, nvic_shcsr 0x20000, nvic_cfsr 0x0, nvic_bfar 0xe000edf8
Error:  SWJ-DP STICKY ERROR
Error:  dcb_dhcsr 0x30003, nvic_shcsr 0x20000, nvic_cfsr 0x0, nvic_bfar 0xe000edf8
Warning:Block read error address 0xfffffff0, count 0x1
Error:  SWJ-DP STICKY ERROR
Error:  dcb_dhcsr 0x30003, nvic_shcsr 0x20000, nvic_cfsr 0x0, nvic_bfar 0xe000edf8
Error:  SWJ-DP STICKY ERROR
Error:  dcb_dhcsr 0x30003, nvic_shcsr 0x20000, nvic_cfsr 0x0, nvic_bfar 0xe000edf8
Error:  SWJ-DP STICKY ERROR
Error:  dcb_dhcsr 0x30003, nvic_shcsr 0x20000, nvic_cfsr 0x0, nvic_bfar 0xe000edf8

My setup: STM32F101C6T6, Amontec JTAGKey, openocd r1180, codesourcery toolchain, ubuntu 8.10 .

ntfreak · November 20, 2008, 10:32pm

could you provide a full debug log?

The changes i made should not be causing a SWJ-DP STICKY ERROR - that normally means the jtag clock is to high.

Cheers

Spen

somers · November 20, 2008, 11:18pm

Here is the log I get when I start openocd, attach gdb, set a breakpoint in a low priority ISR, run to that breakpoint, attempt to single step, and get whisked away into a higher priority ISR, then quit gdb and quit openocd. My clock speed is 36MHz and I get the same results whether I use a JTAG speed of 600Khz or 60KHz.

Debug:   9 0 configuration.c:88 find_file(): found openocd.cfg
Debug:   11 1 command.c:91 script_command(): script_command - interface
Debug:   12 1 command.c:108 script_command(): script_command - interface, argv[0]=ocd_interface
Debug:   13 1 command.c:108 script_command(): script_command - interface, argv[1]=ft2232
Debug:   15 1 command.c:91 script_command(): script_command - ft2232_device_desc
Debug:   16 1 command.c:108 script_command(): script_command - ft2232_device_desc, argv[0]=ocd_ft2232_device_desc
Debug:   17 1 command.c:108 script_command(): script_command - ft2232_device_desc, argv[1]=Amontec JTAGkey A
Debug:   19 1 command.c:91 script_command(): script_command - ft2232_layout
Debug:   20 1 command.c:108 script_command(): script_command - ft2232_layout, argv[0]=ocd_ft2232_layout
Debug:   21 1 command.c:108 script_command(): script_command - ft2232_layout, argv[1]=jtagkey
Debug:   23 1 command.c:91 script_command(): script_command - ft2232_vid_pid
Debug:   24 1 command.c:108 script_command(): script_command - ft2232_vid_pid, argv[0]=ocd_ft2232_vid_pid
Debug:   25 1 command.c:108 script_command(): script_command - ft2232_vid_pid, argv[1]=0x0403
Debug:   26 1 command.c:108 script_command(): script_command - ft2232_vid_pid, argv[2]=0xcff8
Debug:   28 1 command.c:91 script_command(): script_command - jtag_nsrst_delay
Debug:   29 1 command.c:108 script_command(): script_command - jtag_nsrst_delay, argv[0]=ocd_jtag_nsrst_delay
Debug:   30 1 command.c:108 script_command(): script_command - jtag_nsrst_delay, argv[1]=100
Debug:   32 1 command.c:91 script_command(): script_command - jtag_ntrst_delay
Debug:   33 1 command.c:108 script_command(): script_command - jtag_ntrst_delay, argv[0]=ocd_jtag_ntrst_delay
Debug:   34 1 command.c:108 script_command(): script_command - jtag_ntrst_delay, argv[1]=100
Debug:   36 1 command.c:91 script_command(): script_command - reset_config
Debug:   37 1 command.c:108 script_command(): script_command - reset_config, argv[0]=ocd_reset_config
Debug:   38 1 command.c:108 script_command(): script_command - reset_config, argv[1]=trst_and_srst
Debug:   40 1 command.c:91 script_command(): script_command - jtag_device
Debug:   41 1 command.c:108 script_command(): script_command - jtag_device, argv[0]=ocd_jtag_device
Debug:   42 1 command.c:108 script_command(): script_command - jtag_device, argv[1]=4
Debug:   43 1 command.c:108 script_command(): script_command - jtag_device, argv[2]=0x1
Debug:   44 1 command.c:108 script_command(): script_command - jtag_device, argv[3]=0xf
Debug:   45 1 command.c:108 script_command(): script_command - jtag_device, argv[4]=0xe
Debug:   47 1 command.c:91 script_command(): script_command - jtag_device
Debug:   48 1 command.c:108 script_command(): script_command - jtag_device, argv[0]=ocd_jtag_device
Debug:   49 1 command.c:108 script_command(): script_command - jtag_device, argv[1]=5
Debug:   50 1 command.c:108 script_command(): script_command - jtag_device, argv[2]=0x1
Debug:   51 1 command.c:108 script_command(): script_command - jtag_device, argv[3]=0x1
Debug:   52 1 command.c:108 script_command(): script_command - jtag_device, argv[4]=0x1e
Debug:   53 1 target.c:3993 jim_target(): Target command params:
Debug:   54 1 target.c:3994 jim_target(): target cortex_m3 little 0 
Debug:   55 1 target.c:4091 jim_target(): Target OLD SYNTAX - converted to new syntax
Debug:   56 1 target.c:3993 jim_target(): Target command params:
Debug:   57 1 target.c:3994 jim_target(): target create target0 cortex_m3 -endian little -chain-position 0 
Debug:   59 2 command.c:91 script_command(): script_command - working_area
Debug:   60 2 command.c:108 script_command(): script_command - working_area, argv[0]=ocd_working_area
Debug:   61 2 command.c:108 script_command(): script_command - working_area, argv[1]=0
Debug:   62 2 command.c:108 script_command(): script_command - working_area, argv[2]=0x20000000
Debug:   63 2 command.c:108 script_command(): script_command - working_area, argv[3]=16384
Debug:   64 2 command.c:108 script_command(): script_command - working_area, argv[4]=nobackup
Debug:   66 2 command.c:91 script_command(): script_command - bank
Debug:   67 2 command.c:108 script_command(): script_command - bank, argv[0]=ocd_flash_bank
Debug:   68 2 command.c:108 script_command(): script_command - bank, argv[1]=stm32x
Debug:   69 2 command.c:108 script_command(): script_command - bank, argv[2]=0
Debug:   70 2 command.c:108 script_command(): script_command - bank, argv[3]=0
Debug:   71 2 command.c:108 script_command(): script_command - bank, argv[4]=0
Debug:   72 2 command.c:108 script_command(): script_command - bank, argv[5]=0
Debug:   73 2 command.c:108 script_command(): script_command - bank, argv[6]=0
Debug:   75 2 command.c:91 script_command(): script_command - jtag_speed
Debug:   76 2 command.c:108 script_command(): script_command - jtag_speed, argv[0]=ocd_jtag_speed
Debug:   77 2 command.c:108 script_command(): script_command - jtag_speed, argv[1]=100
Debug:   78 2 jtag.c:1965 handle_jtag_speed_command(): handle jtag speed
User:    79 2 command.c:372 command_print(): jtag_speed: 100
Debug:   81 2 command.c:91 script_command(): script_command - init
Debug:   82 2 command.c:108 script_command(): script_command - init, argv[0]=ocd_init
Debug:   83 3 openocd.c:143 handle_init_command(): target init complete
Debug:   84 3 ft2232.c:1382 ft2232_init_ftd2xx(): 'ft2232' interface using FTD2XX with 'jtagkey' layout (0403:cff8)
Debug:   85 131 ft2232.c:1471 ft2232_init_ftd2xx(): current latency timer: 2
Debug:   86 132 ft2232.c:1737 jtagkey_init(): 80 08 1b
Debug:   87 132 ft2232.c:1795 jtagkey_init(): 82 09 0f
Debug:   88 132 ft2232.c:256 ft2232_speed(): 86 64 00
Debug:   89 133 openocd.c:150 handle_init_command(): jtag interface init complete
Debug:   90 133 jtag.c:1625 jtag_init_inner(): Init JTAG chain
Debug:   91 133 jtag.c:327 jtag_call_event_callbacks(): jtag event: JTAG controller reset (TLR or TRST)
Debug:   92 133 jtag.c:1305 jtag_reset_callback(): -
Debug:   93 133 jtag.c:1305 jtag_reset_callback(): -
Debug:   94 133 jtag.c:327 jtag_call_event_callbacks(): jtag event: JTAG controller reset (TLR or TRST)
Debug:   95 133 jtag.c:1305 jtag_reset_callback(): -
Debug:   96 133 jtag.c:1305 jtag_reset_callback(): -
Info:    97 145 jtag.c:1414 jtag_examine_chain(): JTAG device found: 0x3ba00477 (Manufacturer: 0x23b, Part: 0xba00, Version: 0x3)
Info:    98 145 jtag.c:1414 jtag_examine_chain(): JTAG device found: 0x16410041 (Manufacturer: 0x020, Part: 0x6410, Version: 0x1)
Debug:   99 145 jtag.c:327 jtag_call_event_callbacks(): jtag event: JTAG controller reset (TLR or TRST)
Debug:   100 145 jtag.c:1305 jtag_reset_callback(): -
Debug:   101 145 jtag.c:1305 jtag_reset_callback(): -
Debug:   102 147 openocd.c:156 handle_init_command(): jtag init complete
Debug:   103 147 cortex_swjdp.c:968 ahbap_debugport_init():  
Debug:   104 175 cortex_swjdp.c:1012 ahbap_debugport_init(): AHB-AP ID Register 0x14770011, Debug ROM Address 0xe00ff003
Debug:   105 185 target.c:1200 target_read_u32(): address: 0xe000ed00, value: 0x411fc231
Debug:   106 185 cortex_m3.c:1388 cortex_m3_examine(): CORTEX-M3 processor detected
Debug:   107 185 cortex_m3.c:1389 cortex_m3_examine(): cpuid: 0x411fc231
Debug:   108 193 target.c:1200 target_read_u32(): address: 0xe000e004, value: 0x00000001
Debug:   109 201 target.c:1200 target_read_u32(): address: 0xe000e100, value: 0x00040000
Debug:   110 201 cortex_m3.c:1397 cortex_m3_examine(): interrupt enable[0] = 0x00040000
Debug:   111 209 target.c:1200 target_read_u32(): address: 0xe000e104, value: 0x00000120
Debug:   112 209 cortex_m3.c:1397 cortex_m3_examine(): interrupt enable[1] = 0x00000120
Debug:   113 217 target.c:1200 target_read_u32(): address: 0xe0002000, value: 0x00000261
Debug:   114 217 cortex_m3.c:1412 cortex_m3_examine(): FPB fpcr 0x261, numcode 6, numlit 2
Debug:   115 225 target.c:1200 target_read_u32(): address: 0xe0001000, value: 0x40000000
Debug:   116 225 openocd.c:159 handle_init_command(): jtag examine complete
Debug:   117 226 openocd.c:165 handle_init_command(): flash init complete
Debug:   118 226 openocd.c:169 handle_init_command(): mflash init complete
Debug:   119 226 openocd.c:173 handle_init_command(): NAND init complete
Debug:   120 226 openocd.c:177 handle_init_command(): pld init complete
Warning: 121 226 telnet_server.c:614 telnet_init(): no telnet port specified, using default port 4444
Warning: 122 226 gdb_server.c:2184 gdb_init(): no gdb port specified, using default port 3333
Debug:   123 226 gdb_server.c:2205 gdb_init(): gdb service for target cortex_m3 at port 3333
Warning: 124 226 tcl_server.c:178 tcl_init(): no tcl port specified, using default port 6666
Info:    125 25936 server.c:84 add_connection(): accepting 'telnet' connection from 0
Info:    126 31946 server.c:396 server_loop(): dropped 'telnet' connection
Info:    127 60189 server.c:84 add_connection(): accepting 'gdb' connection from 0
Debug:   128 60189 cortex_m3.c:483 cortex_m3_halt(): target->state: halted
Debug:   129 60189 cortex_m3.c:487 cortex_m3_halt(): target was already halted
Debug:   130 60197 target.c:717 target_call_event_callbacks(): target event 26 (gdb-attach)
Debug:   131 60197 target.c:3125 target_handle_event(): event: 26 gdb-attach - no action
Debug:   132 60197 target.c:3125 target_handle_event(): event: 26 gdb-attach - no action
Debug:   133 60197 gdb_server.c:2033 gdb_input_inner(): received packet: 'qSupported'
Warning: 134 60197 gdb_server.c:567 gdb_get_packet_inner(): acknowledgment received, but no packet pending
Debug:   135 60197 gdb_server.c:2033 gdb_input_inner(): received packet: '?'
User:    136 60197 gdb_server.c:100 gdb_last_signal(): undefined debug reason 6 - target needs reset
Debug:   137 60197 gdb_server.c:2033 gdb_input_inner(): received packet: 'Hc-1'
Debug:   138 60197 gdb_server.c:2033 gdb_input_inner(): received packet: 'qC'
Debug:   139 60198 gdb_server.c:2033 gdb_input_inner(): received packet: 'qOffsets'
Debug:   140 60198 gdb_server.c:2033 gdb_input_inner(): received packet: 'Hg0'
Debug:   141 60198 gdb_server.c:2033 gdb_input_inner(): received packet: 'g'
Debug:   142 60198 gdb_server.c:2033 gdb_input_inner(): received packet: 'qXfer:memory-map:read::0,fff'
Debug:   143 60207 target.c:1200 target_read_u32(): address: 0xe0042000, value: 0x20036410
Info:    144 60207 stm32x.c:706 stm32x_probe(): device id = 0x20036410
Debug:   145 60217 target.c:1225 target_read_u16(): address: 0x1ffff7e0, value: 0x0020
Info:    146 60217 stm32x.c:751 stm32x_probe(): flash size = 32kbytes
Debug:   147 60218 gdb_server.c:2033 gdb_input_inner(): received packet: 'm0,4'
Debug:   148 60218 gdb_server.c:1173 gdb_read_memory_packet(): addr: 0x00000000, len: 0x00000004
Debug:   149 60218 target.c:1065 target_read_buffer(): reading buffer of 4 byte at 0x00000000
Debug:   150 67778 gdb_server.c:2033 gdb_input_inner(): received packet: 'Z1,8000f2c,2'
Debug:   151 67778 gdb_server.c:1368 gdb_breakpoint_watchpoint_packet(): -
Debug:   152 67778 target.c:1268 target_write_u32(): address: 0xe0002008, value: 0x48000f2d
Debug:   153 67787 cortex_m3.c:870 cortex_m3_set_breakpoint(): fpc_num 0 fpcr_value 0x48000f2d
Debug:   154 67787 breakpoints.c:93 breakpoint_add(): added hardware breakpoint at 0x08000f2c of length 0x00000002
Debug:   155 67787 gdb_server.c:2033 gdb_input_inner(): received packet: 'vCont?'
Debug:   156 67787 gdb_server.c:2033 gdb_input_inner(): received packet: 'Hc0'
Debug:   157 67787 gdb_server.c:2033 gdb_input_inner(): received packet: 'c'
Debug:   158 67787 target.c:717 target_call_event_callbacks(): target event 9 (gdb-start)
Debug:   159 67787 target.c:3125 target_handle_event(): event: 9 gdb-start - no action
Debug:   160 67787 target.c:3125 target_handle_event(): event: 9 gdb-start - no action
Debug:   161 67787 gdb_server.c:1332 gdb_step_continue_packet(): -
Debug:   162 67787 gdb_server.c:1346 gdb_step_continue_packet(): continue
Debug:   163 67787 target.c:3125 target_handle_event(): event: 3 old-pre_resume - no action
Debug:   164 67787 armv7m.c:134 armv7m_restore_context():  
Debug:   165 67797 target.c:717 target_call_event_callbacks(): target event 6 (resumed)
Debug:   166 67797 target.c:3125 target_handle_event(): event: 6 resumed - no action
Debug:   167 67797 target.c:3125 target_handle_event(): event: 6 resumed - no action
Debug:   168 67797 cortex_m3.c:636 cortex_m3_resume(): target resumed at 0x1
Debug:   169 67817 cortex_m3.c:336 cortex_m3_debug_entry():  
Debug:   170 67839 cortex_m3.c:132 cortex_m3_clear_halt():  NVIC_DFSR 0x3
Debug:   171 67871 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 0  value 0x15
Debug:   172 67893 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 1  value 0x20000604
Debug:   173 67915 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 2  value 0x150000
Debug:   174 67937 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 3  value 0x119dad
Debug:   175 67959 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 4  value 0x20000086
Debug:   176 67981 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 5  value 0x0
Debug:   177 68005 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 6  value 0x0
Debug:   178 68027 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 7  value 0x2000059c
Debug:   179 68049 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 8  value 0x20000054
Debug:   180 68071 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 9  value 0x20000290
Debug:   181 68093 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 10  value 0xf2981eba
Debug:   182 68115 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 11  value 0xd23f63ed
Debug:   183 68137 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 12  value 0x0
Debug:   184 68159 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 13  value 0x20001798
Debug:   185 68181 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 14  value 0x0
Debug:   186 68203 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 15  value 0x8000f2c
Debug:   187 68225 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 16  value 0x21000038
Debug:   188 68247 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 17  value 0x20001798
Debug:   189 68269 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 18  value 0x5a96f7d8
Debug:   190 68291 cortex_m3.c:1206 cortex_m3_load_core_reg_u32(): load from special reg 19 value 0x0
Debug:   192 68313 cortex_m3.c:1206 cortex_m3_load_core_reg_u32(): load from special reg 20 value 0x0
Debug:   193 68335 cortex_m3.c:1206 cortex_m3_load_core_reg_u32(): load from special reg 21 value 0x0
Debug:   194 68357 cortex_m3.c:1206 cortex_m3_load_core_reg_u32(): load from special reg 22 value 0x0
Debug:   195 68367 cortex_m3.c:321 cortex_m3_examine_exception_reason(): External Interrupt(40) SHCSR 0x20000, SR 0x0, CFSR 0xffffffff, AR 0xffffffff
Debug:   196 68367 cortex_m3.c:398 cortex_m3_debug_entry(): entered debug state in core mode: Handler at PC 0x8000f2c, target->state: halted
Debug:   197 68367 target.c:717 target_call_event_callbacks(): target event 4 (early-halted)
Debug:   198 68367 target.c:3125 target_handle_event(): event: 4 early-halted - no action
Debug:   199 68367 target.c:3125 target_handle_event(): event: 4 early-halted - no action
Debug:   200 68368 target.c:717 target_call_event_callbacks(): target event 5 (halted)
Debug:   201 68368 target.c:3125 target_handle_event(): event: 5 halted - no action
Debug:   202 68368 target.c:3125 target_handle_event(): event: 5 halted - no action
Debug:   203 68368 target.c:717 target_call_event_callbacks(): target event 10 (gdb-end)
Debug:   204 68368 target.c:3125 target_handle_event(): event: 10 gdb-end - no action
Debug:   205 68368 target.c:3125 target_handle_event(): event: 10 gdb-end - no action
Debug:   206 68368 gdb_server.c:2033 gdb_input_inner(): received packet: 'g'
Debug:   207 68368 gdb_server.c:2033 gdb_input_inner(): received packet: 'z1,8000f2c,2'
Debug:   208 68368 gdb_server.c:1368 gdb_breakpoint_watchpoint_packet(): -
Debug:   209 68368 target.c:1268 target_write_u32(): address: 0xe0002008, value: 0x00000000
Debug:   210 68378 gdb_server.c:2033 gdb_input_inner(): received packet: 'm8000f2c,4'
Debug:   211 68378 gdb_server.c:1173 gdb_read_memory_packet(): addr: 0x08000f2c, len: 0x00000004
Debug:   212 68378 target.c:1065 target_read_buffer(): reading buffer of 4 byte at 0x08000f2c
Debug:   213 69195 gdb_server.c:2033 gdb_input_inner(): received packet: 'Hc0'
Debug:   214 69195 gdb_server.c:2033 gdb_input_inner(): received packet: 's'
Debug:   215 69195 target.c:717 target_call_event_callbacks(): target event 9 (gdb-start)
Debug:   216 69195 target.c:3125 target_handle_event(): event: 9 gdb-start - no action
Debug:   217 69195 target.c:3125 target_handle_event(): event: 9 gdb-start - no action
Debug:   218 69195 gdb_server.c:1332 gdb_step_continue_packet(): -
Debug:   219 69195 gdb_server.c:1352 gdb_step_continue_packet(): step
Debug:   220 69195 armv7m.c:134 armv7m_restore_context():  
Debug:   221 69195 target.c:717 target_call_event_callbacks(): target event 6 (resumed)
Debug:   222 69195 target.c:3125 target_handle_event(): event: 6 resumed - no action
Debug:   223 69195 target.c:3125 target_handle_event(): event: 6 resumed - no action
Debug:   224 69210 cortex_m3.c:688 cortex_m3_step(): target stepped dcb_dhcsr = 0x1030007 nvic_icsr = 0x0
Debug:   225 69210 cortex_m3.c:336 cortex_m3_debug_entry():  
Debug:   226 69232 cortex_m3.c:132 cortex_m3_clear_halt():  NVIC_DFSR 0x1
Debug:   227 69264 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 0  value 0x15
Debug:   228 69286 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 1  value 0x20000604
Debug:   229 69309 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 2  value 0x150000
Debug:   230 69331 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 3  value 0x119dad
Debug:   231 69353 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 4  value 0x20000086
Debug:   232 69375 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 5  value 0x0
Debug:   233 69397 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 6  value 0x0
Debug:   234 69419 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 7  value 0x2000059c
Debug:   235 69441 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 8  value 0x20000054
Debug:   236 69463 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 9  value 0x20000290
Debug:   237 69485 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 10  value 0xf2981eba
Debug:   238 69507 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 11  value 0xd23f63ed
Debug:   239 69529 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 12  value 0x0
Debug:   240 69551 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 13  value 0x20001778
Debug:   241 69573 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 14  value 0xfffffff1
Debug:   242 69595 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 15  value 0x800029c
Debug:   243 69617 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 16  value 0x21000022
Debug:   244 69641 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 17  value 0x20001778
Debug:   245 69663 cortex_m3.c:1180 cortex_m3_load_core_reg_u32(): load from core reg 18  value 0x5a96f7d8
Debug:   246 69685 cortex_m3.c:1206 cortex_m3_load_core_reg_u32(): load from special reg 19 value 0x0
Debug:   248 69707 cortex_m3.c:1206 cortex_m3_load_core_reg_u32(): load from special reg 20 value 0x0
Debug:   249 69729 cortex_m3.c:1206 cortex_m3_load_core_reg_u32(): load from special reg 21 value 0x0
Debug:   250 69751 cortex_m3.c:1206 cortex_m3_load_core_reg_u32(): load from special reg 22 value 0x0
Debug:   251 69761 cortex_m3.c:321 cortex_m3_examine_exception_reason(): External Interrupt(18) SHCSR 0x20000, SR 0x0, CFSR 0xffffffff, AR 0xffffffff
Debug:   252 69761 cortex_m3.c:398 cortex_m3_debug_entry(): entered debug state in core mode: Handler at PC 0x800029c, target->state: halted
Debug:   253 69761 target.c:717 target_call_event_callbacks(): target event 4 (early-halted)
Debug:   254 69761 target.c:3125 target_handle_event(): event: 4 early-halted - no action
Debug:   255 69761 target.c:3125 target_handle_event(): event: 4 early-halted - no action
Debug:   256 69761 target.c:717 target_call_event_callbacks(): target event 5 (halted)
Debug:   257 69761 target.c:3125 target_handle_event(): event: 5 halted - no action
Debug:   258 69761 target.c:3125 target_handle_event(): event: 5 halted - no action
Debug:   259 69761 target.c:717 target_call_event_callbacks(): target event 10 (gdb-end)
Debug:   260 69761 target.c:3125 target_handle_event(): event: 10 gdb-end - no action
Debug:   261 69761 target.c:3125 target_handle_event(): event: 10 gdb-end - no action
Debug:   262 69761 cortex_m3.c:693 cortex_m3_step(): target stepped dcb_dhcsr = 0x30003 nvic_icsr = 0x0
Debug:   263 69761 gdb_server.c:2033 gdb_input_inner(): received packet: 'g'
Debug:   264 69765 gdb_server.c:2033 gdb_input_inner(): received packet: 'm800029c,4'
Debug:   265 69765 gdb_server.c:1173 gdb_read_memory_packet(): addr: 0x0800029c, len: 0x00000004
Debug:   266 69765 target.c:1065 target_read_buffer(): reading buffer of 4 byte at 0x0800029c
Debug:   267 69775 gdb_server.c:2033 gdb_input_inner(): received packet: 'mfffffff0,4'
Debug:   268 69775 gdb_server.c:1173 gdb_read_memory_packet(): addr: 0xfffffff0, len: 0x00000004
Debug:   269 69775 target.c:1065 target_read_buffer(): reading buffer of 4 byte at 0xfffffff0
Debug:   270 69783 cortex_swjdp.c:228 swjdp_transaction_endcheck(): swjdp: CTRL/STAT error 0xf0000021
Error:   271 69783 cortex_swjdp.c:242 swjdp_transaction_endcheck(): SWJ-DP STICKY ERROR
Debug:   272 69787 cortex_swjdp.c:250 swjdp_transaction_endcheck(): swjdp: status 0xf0000001
Error:   273 69825 cortex_swjdp.c:257 swjdp_transaction_endcheck(): dcb_dhcsr 0x30003, nvic_shcsr 0x20000, nvic_cfsr 0x0, nvic_bfar 0xe000edf8
Debug:   274 69835 cortex_swjdp.c:228 swjdp_transaction_endcheck(): swjdp: CTRL/STAT error 0xf0000021
Error:   275 69835 cortex_swjdp.c:242 swjdp_transaction_endcheck(): SWJ-DP STICKY ERROR
Debug:   276 69839 cortex_swjdp.c:250 swjdp_transaction_endcheck(): swjdp: status 0xf0000001
Error:   277 69877 cortex_swjdp.c:257 swjdp_transaction_endcheck(): dcb_dhcsr 0x30003, nvic_shcsr 0x20000, nvic_cfsr 0x0, nvic_bfar 0xe000edf8
Warning: 278 69877 cortex_swjdp.c:725 ahbap_read_buf_u32(): Block read error address 0xfffffff0, count 0x1
Debug:   279 69877 gdb_server.c:2033 gdb_input_inner(): received packet: 'md23f63ed,4'
Debug:   280 69877 gdb_server.c:1173 gdb_read_memory_packet(): addr: 0xd23f63ed, len: 0x00000004
Debug:   281 69877 target.c:1065 target_read_buffer(): reading buffer of 4 byte at 0xd23f63ed
Debug:   282 69887 cortex_swjdp.c:228 swjdp_transaction_endcheck(): swjdp: CTRL/STAT error 0xf0000021
Error:   283 69887 cortex_swjdp.c:242 swjdp_transaction_endcheck(): SWJ-DP STICKY ERROR
Debug:   284 69891 cortex_swjdp.c:250 swjdp_transaction_endcheck(): swjdp: status 0xf0000001
Error:   285 69929 cortex_swjdp.c:257 swjdp_transaction_endcheck(): dcb_dhcsr 0x30003, nvic_shcsr 0x20000, nvic_cfsr 0x0, nvic_bfar 0xe000edf8
Debug:   286 69939 cortex_swjdp.c:228 swjdp_transaction_endcheck(): swjdp: CTRL/STAT error 0xf0000021
Error:   287 69939 cortex_swjdp.c:242 swjdp_transaction_endcheck(): SWJ-DP STICKY ERROR
Debug:   288 69943 cortex_swjdp.c:250 swjdp_transaction_endcheck(): swjdp: status 0xf0000001
Error:   289 69981 cortex_swjdp.c:257 swjdp_transaction_endcheck(): dcb_dhcsr 0x30003, nvic_shcsr 0x20000, nvic_cfsr 0x0, nvic_bfar 0xe000edf8
Debug:   290 69991 cortex_swjdp.c:228 swjdp_transaction_endcheck(): swjdp: CTRL/STAT error 0xf0000021
Error:   291 69991 cortex_swjdp.c:242 swjdp_transaction_endcheck(): SWJ-DP STICKY ERROR
Debug:   292 69995 cortex_swjdp.c:250 swjdp_transaction_endcheck(): swjdp: status 0xf0000001
Error:   293 70033 cortex_swjdp.c:257 swjdp_transaction_endcheck(): dcb_dhcsr 0x30003, nvic_shcsr 0x20000, nvic_cfsr 0x0, nvic_bfar 0xe000edf8
Debug:   294 74994 gdb_server.c:2033 gdb_input_inner(): received packet: 'k'
Debug:   295 74995 target.c:717 target_call_event_callbacks(): target event 10 (gdb-end)
Debug:   296 74995 target.c:3125 target_handle_event(): event: 10 gdb-end - no action
Debug:   297 74995 target.c:717 target_call_event_callbacks(): target event 27 (gdb-detach)
Debug:   298 74995 target.c:3125 target_handle_event(): event: 27 gdb-detach - no action
Info:    299 74995 server.c:396 server_loop(): dropped 'gdb' connection

ntfreak · November 21, 2008, 11:17am

somers,

the sticky error is caused by gdb trying to read address 0xfffffff0 - probably trying to trace a stack or something so can be ignored - we are aware of this one.

The patch i committed will only preserve the state of C_MASKINTS - it does not do anything with it.

I just tried a demo project similar to yours - two interrupts one with a higher priority.

a breakpoint was set in the lower priority int i then masked the ints using:

mon mww 0xE000EDF0 0xa05f000b

performed s step and stayed in the low prority interrupt.

restored the ints by using

mon mww 0xE000EDF0 0xa05f0003

Cheers

Spen

ntfreak · November 21, 2008, 2:29pm

To make thing a little easier i have added a new cmd to openocd:

cortex_m3 maskisr on - will mask interrupts, off to resume normal interrupts.

Cheers

Spen

CoupeDLX · November 21, 2008, 9:34pm

I updated the patch to work with the latest SVN (1181). What mailing list should I send this to?

$ svn diff target/cortex_m3.c
Index: target/cortex_m3.c
===================================================================
--- target/cortex_m3.c  (revision 1181)
+++ target/cortex_m3.c  (working copy)
@@ -675,7 +675,9 @@
        armv7m_restore_context(target);
 
        target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
-
+
+   /* ensure ints are masked when we step */
+       cortex_m3_write_debug_halt_mask(target, C_MASKINTS, 0);
        /* set step and clear halt */
        cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
        ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);

ntfreak · November 22, 2008, 11:39am

The openocd mailing list details are here:

https://lists.berlios.de/mailman/listin … evelopment

I am a admin on openocd so your patch will need approval anyway.

The problem with your patch is we cannot always mask interrupts during step - we may not want to.

This is the reason i have added the new cmd above - it caters for both cases.

also we have the issue of gdb performing a asm or c step - they mean very different things. a c step may include a resume plus a breakpoint.

Cheers

Spen

somers · November 22, 2008, 10:39pm

ntfreak, your new code in r1181 does exactly what it should. Thanks for the help.

CoupeDLX · November 24, 2008, 3:38am

In what situations do you want to step and not mask interrupts? How can we tell the difference when GDB asks the system to step? Are we totally out of luck without changing GDB to send a command to turn interrupts on/off?

I want to be able to step from GDB without manually turning interrupts off manually and trying to remember to turn them back on before continuing.

Thanks for the help. I am very impressed with the tool overall and would like to help polish the edges wherever I can.

CoupeDLX · November 24, 2008, 7:15pm

I have added the following to my gdb init script and everything is working exactly as I want with version 1183, your fix is the exact right thing to do here, once the user knows how to use GDB:-)

Thanks a lot for the help.

symbol-file code.elf
target remote localhost:3333
#turn off timers and peripherals while we are stopped
mon mww 0xe0042004 0x1fff00
#mask interupts when we stop, re-enable when we turn back on.
define hook-stop
mon cortex_m3 maskisr on
end
define hook-continue
mon cortex_m3 maskisr off
end
#run to main
b main
c

somers · December 9, 2008, 6:33pm

Unfortunately, C_MASKINTS masks interrupts during run as well as step. In my experience, this is seldom what you want. Looking at the cortex m3 reference manual, I don’t see any way to mask interrupts during step only. So this is my workaround: I define aliases in gdb that turn C_MASKINTS off when I’m running and turn it back on when I’m stepping. I put the following code in extra/ldm0.gdb and when I start gdb, I source it.

target remote localhost:3333
symbol-file build/main.elf

define cc
  ss
  mon cortex_m3 maskisr off
  c
  end

define ss
  mon cortex_m3 maskisr on
  s
  end

define nn
  mon cortex_m3 maskisr on
  n
  end

One other irritant with the core is that when I am halted outside of an ISR, the timer ISR queues up. So when I continue, my chip will service the timer ISR and then halt when that ISR returns. So I ended up halted at the same instruction I started at. This means that in order to use breakpoints outside of ISRs, I basically have to delete them and recreate them every time I use it. The first ‘ss’ in my cc command works around this. It steps past the breakpoint (outside of the ISR) then continues. That way, when the ISR returns it returns to a point past my breakpoint.

If anybody has found a more elegant solution to either of these problems, I would be interested to know.

CoupeDLX · December 9, 2008, 6:42pm

I think the gdb hook definitions I gave in my previous post will do exactly what you are trying to do while still using just continue and step.

Those commands mask ISRs whenever the system is stopped and un-mask whenever you type continue.

To solve the timer queuing problem I stop all the peripherals when stopped in the debugger. (the set of e0042004).

I have been using this setup for a couple of weeks now for my day-to-day development and it has been working very well.

somers · December 9, 2008, 10:20pm

Silly me, not reading the thread carefully. As they say, a few months in the laboratory can often save a few hours in the library.

gds · June 4, 2009, 10:29pm

CoupeDLX:

symbol-file code.elf

target remote localhost:3333
#turn off timers and peripherals while we are stopped
mon mww 0xe0042004 0x1fff00
#mask interupts when we stop, re-enable when we turn back on.
define hook-stop
mon cortex_m3 maskisr on
end
define hook-continue
mon cortex_m3 maskisr off
end
#run to main
b main
c

It’s been a while since this post was written but I was wondering if the command to “turn off timers and peripherals while we are stopped” should be inside the hook-stop macro and a corresponding command to turn them on should be inside hook-continue??

gds · June 5, 2009, 12:45pm

gds:
It’s been a while since this post was written but I was wondering if the command to “turn off timers and peripherals while we are stopped” should be inside the hook-stop macro and a corresponding command to turn them on should be inside hook-continue??

I should have looked in the Cortex-M3 reference guide before writing this. I now see that this enables the processor to turn off these signal when it is stopped.

mathen · June 5, 2009, 1:08pm

Hello,

i try to debug the svc command on a cortex m3 but the cpu only stay on the same command and dont jump to the exception handler. This happens in single step or continue mode without any error message. If i start the application without a debugger the svc call works fine.

Tested openocd versions:

0.1.0 release
svn:2075

Any hints ?

Thanks!

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Can't mask interrupts during step with OpenOCD and cortex-m3

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