Clarify clearance

Archive BatchPCB
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I’ve been an electronics hobbyist forever, and I’ve made a few through hole boards using the predecessor to batchpcb, and I’ve done some soldering of SMD parts; so now I’m contemplating a PCB using a device with very fine spacing of lands. The package is called HVQFN - 44. The lands are 0.5 mm pitch with 0.3 gap between lands. This translates to a gap between the copper lands of ~10 mils, which appears to satisfy the rules of 8 mils minimum clearance.

The question is in the solder resist layer. The gap between the lands for the resist layer is about 2 mils. Will this pass the design rule checker? Is this a reasonable candidate for batchpcb? Anything I should be doing here?

Jake

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eejake52:
The gap between the lands for the resist layer is about 2 mils. Will this pass the design rule checker? Is this a reasonable candidate for batchpcb? Anything I should be doing here?

Jake,

One way to find out is to submit a design using this geometry and see if it passes the DRCbot. One could create a test vehicle with this part and a few min. space traces and clearances in just a few minutes, compile and zip it and sent it over to BatchPCB for inspection.

Comments Welcome!

Peter

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eejake52:
The gap between the lands for the resist layer is about 2 mils. Will this pass the design rule checker?

Jake

You can apply any design rules you like, but in the real world you are not going to get a solder mask trace of 2 thou!

Think about it, solder masks are applied using silk screens and even the finest of meshes will not give you a gap that small to apply a mask to a board.

For components of the pitch you are talking about, you are going to get a strip solder mask window the size of the row of pins.

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bigglez:
One way to find out is to submit a design using this geometry and see if it passes the DRCbot.

Tried that today (2006-Nov-04), but it’s been over 12 hours and I haven’t got a response. Is the system down today?

Jake

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For anyone following this thread. The DRC bot did pass the footprint (yay!).

Also, the batchpcb system behaved as expected; I just didn’t see the response when it arrived because my spam filter hadn’t been told about that sender.

I’ve almost got the rest of board laid out. I’ll post back when the boards come in (which will almost be certainly in the new year, due to shipping, customs, etc.).

Jake

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I was close to asking about soldermask limits myself, so I’ll just try to add to, and ask for clarifications to, this thread:

  1. In the BatchPCB faq, at first we are told “8mil spacing minimum” and “8mil traces minimum” as separate items, and further down “minimum trace width is 8mil with 8 mil spacing”. Are “spacing” and “traces” meant to be general, i.e. in reference to soldermask and/or visible silkscreen as well?

My best guess at this point: “officially yes”, because all features are applied using silkscreens of the same resolution (?); “unofficially no”, because it seems that the DRC bot doesn’t care about non-trace minimums (since Jake reports above that a soldermask with 2 mil spacing passes, IIUC).

  1. The only previous thread I could find that touches on this whole topic is from April: http://www.sparkfun.com/cgi-bin/phpbb/v … php?t=2884 . From part of this, I understand that an equally important limit for choosing soldermask parameters is the maximum registration (i.e. relative placement) error between the different screens. E.g. if this is, say, 4 mil (?), then that’s what should be used for the soldermask “stop” value (i.e. the gap around a pad before the soldermask starts). The thread from April didn’t arrive at any recommended limits, although someone noted “…the solder mask registration problems I have read about”. So, do we have a value for maximum registration error?

-Terry

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terryk91:

  1. In the BatchPCB faq, at first we are told “8mil spacing minimum” and “8mil traces minimum” as separate items, and further down “minimum trace width is 8mil with 8 mil spacing”. Are “spacing” and “traces” meant to be general, i.e. in reference to soldermask and/or visible silkscreen as well?

So, do we have a value for maximum registration error?

Terry,

This is an age-old PCB design confusion. Basically, the minimum spec is an agreement between board designer (you) and the factory that makes the boards. Like most products, quality varies, and reasonable limits must be set to make the project a success.

In the PCB world the factory wants to reduce scrap, rework, and returns. So they like wide specs. As board designers we like to go in the other direction! Factories are under competitive pressure, too.

The traces are formed by etching and many variables affect if the metal is over or under etched, thus making “8mil” the accepted minimum remaining width for the SFE service. The resulting trace is protected during etching by the tin (or solder) plating which is done over photographically exposed and developed copper clad boards, and as you point out, has it’s own tolerances for alignment and widths.

The other spec is spacing, or gap from metal to metal, which is also 8mil in this service. Under etching or under exposure of the photo resist will reduce this space, risking shorts (or leakage).

As you point out there are many steps in the process that require alignment. I’ve seen some boards (not SFE) with the holes off the center of the pads. With small holes and big pads this isn’t too bad. I’ve experimented with changing the “restring” settings in EAGLE and SFE made boards with well-centered holes in tiny pads. I was impressed!

There’s a third party involved, SFE is the broker, and to keep us (and the factory) happy they reject anything we design outside of their limits. As a practical matter the BatchPCB bot has slightly different settings to reduce the possibility of rejecting designs made right on the limit boundary.

I suspect the factory can do better than 8mil traces and 8mil spaces, but the yields may be lower resulting in rejects. Ouch!

The bottom line is that designing within the published spec will assure success, bending the rules can be done but don’t be too surprised is the bot kicks it out or the boards have problems later. Also, reorders may not do as well as the prototypes due to rule abuse.

Comments Welcome!

Comments Welcome!

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Peter, I believe you’ve misunderstood my post. I am not asking what the design limits or the DRC bot are for. Nor am I asking about the possibility of pushing the limits for traces (implied copper).

In question “1”, I am asking for a clarification to the published limits (i.e. do they include non-trace (i.e. non-copper) features).

When I said that the answer to “1” may be “unofficially no”, that only implies that we may be able to push those limits for non-copper-trace features, since that’s much less likely to result in a failed board. (E.g. you may just get a “wispy” soldermask or visible silkscreen.) (Of course, if you put a non-trace feature too close to a pad, a large registration error may put it on top of the pad.) But this is tangential to an actual answer to “1”.

In question “2”, I am asking for information on an additional limit (i.e. the maximum registration error).

-Terry

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terryk91:
Peter, I believe you’ve misunderstood my post.

…

In question “1”, I am asking for a clarification to the published limits (i.e. do they include non-trace (i.e. non-copper) features).

…

(E.g. you may just get a “wispy” soldermask or visible silkscreen.) (Of course, if you put a non-trace feature too close to a pad, a large registration error may put it on top of the pad.) But this is tangential to an actual answer to “1”.

In question “2”, I am asking for information on an additional limit (i.e. the maximum registration error).

Terry,

Thanks for the clarification of your question. On non-conductor features, such as silk-screen, the limit is 8mil. (This is why the EAGLE default of 6mil is risky - and may result in lost or broken lettering - and Silk-Gen.ULP fixes it).

I suspect (but can’t prove) that conductor features are subtracted from silk screen layers to prevent the ink from touching the exposed solder.

I often allow text to overlap solder (usually vias), knowing it will be lost during manufacture. (Ironically, I don’t have any SFE boards in front of me today to confirm this…)

What might be useful is to run a test coupon through the service and measure the limits. A resolution wedge would quickly indicate the limits of the process. It would be fair to run it periodically to measure consistency.

Comments Welcome!

Peter

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I think that’s a great idea. Sparky, could you possibly do that and put a picture up? I would be hugely helpful.

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bigglez:
On non-conductor features, such as silk-screen, the limit is 8mil.

You’re stating that “as given”, so I assume that means it is usual to take the “non-copper” limits as the same as the copper limits. So I expect that’s obvious to people familiar with PCB manufacture. (Again, I am wondering if this is due to using the same resolution masks for all features.)

If this isn’t obvious, or, simply because there’ll be people here at all points of the learning curve, it should be clarified in the BatchPCB faq, no? (Is this where I say “Sparky?”)

bigglez:
I suspect (but can’t prove) that conductor features are subtracted from silk screen layers to prevent the ink from touching the exposed solder.

I often allow text to overlap solder (usually vias), knowing it will be lost during manufacture. (Ironically, I don’t have any SFE boards in front of me today to confirm this…)

Note: in this thread from January: http://www.sparkfun.com/cgi-bin/phpbb/v … php?t=2233, the poster cautioned us to not even mistakenly have silkscreen on pads since it would still appear, i.e. a subtraction was not done.

bigglez:
What might be useful is to run a test coupon through the service and measure the limits. A resolution wedge would quickly indicate the limits of the process. It would be fair to run it periodically to measure consistency.

Who knows, BatchPCB may already be doing that. I’m not sure they would post such a test (as suggested by “Philba” above) since it may encourage people to push the limits for copper features.

Hmmm… one could also include a test for registration error (by having appropriate shapes of copper, soldermask, and visible silkscreen that are supposed to line up somehow). Sort of like an inkjet alignment test!

In the meantime, do we have a figure for maximum registration error, or is this also something commonly understood? E.g. 3 or 4 mil? 25% of the copper limit of 8 mil? Surely it doesn’t depend on whether someone remembered to put on their glasses?

Holy traces, Batman - I just noticed that further down in the very thread I ref above, Sparky says: “On a scale of 0-5 stars, I’d give GP 4 stars. They are really good, but some of the US domestic PCB that have much better aligned soldermask/silkscreens.”

I.e. an indication of the degree of registration error (somehow I missed this in my earlier reading). Has this situation improved?

I’m only working on my 1st design so don’t have an idea of typical results. What are people’s experience with this from BatchPCB? (But again, shouldn’t this be in the faq, in the form of a number?!)

-Terry

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terryk91:
I’m only working on my 1st design so don’t have an idea of typical results. What are people’s experience with this from BatchPCB? (But again, shouldn’t this be in the faq, in the form of a number?!)

Terry,

First design? With BatchPCB or in general? Perhaps you are over-thinking the process…

I’m delighted with the handful of different boards I’ve done through BatchPCB. I’ve submitted designs with 8mil spacing and 24mil diameter holes, and the results have been outstanding.

As long as you don’t push your expectations (by staying within the simple guidelines as implemented by the BatchPCB bot) I think that you will be delighted too!

Comments Welcome!

Peter

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bigglez:
First design? With BatchPCB or in general? Perhaps you are over-thinking the process…

?! Trying to discuss issues of fine soldermasks = over-thinking ...

For concreteness, I have a similar situation to Jake above (trying to spec a fine soldermask, just not quite so fine as his), which is why I’ve been asking about non-copper limits, as well as alignment error (what I’ve previously been calling “registration”).

Thus, I’m trying to discuss actual recommendations for these values, and am hoping those with info or experience will chime in. (Yes, Peter, I know you’ve already stated your belief that the non-copper limit is 8 mil.)

If I can spec a fine soldermask, why not? (It’s just a parameter in my footprint defs.)

Spec’ing, say, a soldermask with 6 mil “traces” between the pads may not be recommended nor give great results (?), but in itself wouldn’t be a problem for a prototype board. However, with the space between the soldermask and pads (the “stop value”) being, say, 3 mil, it would be a headache if the alignment were so bad such that the soldermask overlapped the pads. (And so wouldn’t be worth doing.)

So, for a fine soldermask, it would seem that the alignment is critical, and I would like to hear more, especially given Sparky’s comment in the thread I referred to above (“…some of the US domestic PCB that have much better aligned soldermask/silkscreens.”)

bigglez:
I’m delighted with the handful of different boards I’ve done through BatchPCB. I’ve submitted designs with 8mil spacing and 24mil diameter holes, and the results have been outstanding.

Did it have a soldermask? If so, what was the alignment like? (When I asked about "typical results", it was in the context of alignment.) Er, anyone else?
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terryk91:

bigglez:
First design? With BatchPCB or in general? Perhaps you are over-thinking the process…

?! Trying to discuss issues of fine soldermasks = over-thinking ...

If the OP was/is doing his first PCB then I’d say this discussion of process limits is indeed overthinking the problem. From my experience, no matter how long I stare at the design in EAGLE, seeing the real PCB is the ultimate test of success! Getting the first PCB out and back from fab was an important step for me…

Comments Welcome!

Peter

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terryk91:
Thus, I’m trying to discuss actual recommendations for these values, and am hoping those with info or experience will chime in. (Yes, Peter, I know you’ve already stated your belief that the non-copper limit is 8 mil.)

If I can spec a fine soldermask, why not? (It’s just a parameter in my footprint defs.)

Terry91 et al.,

In reality there are no limits to this process - just probability of success.

The PCB shop (in China) has to turn out enough “good” boards to cover the costs and lost time of “bad” boards.

To this end the Gold Phoenix website states: Minimum clearance and trace width 7mil, minimum hole size 15mil. And goes on to give price premiums for 4, 5, and 6mil trace widths and clearance. More info here: http://tinyurl.com/y27zcx Notice that they predict a failure rate of 15%!

What this tells me is that the PCB shop can do better than BatchPCB, who have likely padded the specs to improve yields and reduce prices (and gain momentum from more projects with standard instead of special limits).

This is all well and good and the result is the BatchPCB service we have today.

Unfortunately for me, one of my last BatchPCB jobs was placed on B/O yesterday due to “One board did not pass QC, will ship it when it arrives in 1-2 weeks. Thanks.”

Has anyone else had this happen to their projects?

Comments Welcome!

Peter