Does anyone have any advice for creating complex (ie not rectangular) pads when creating a new package in the library?
Specifically, I’m looking at the TI TPS6300x chips ([datasheet) which come in a powerpad package. I’ve tried creating the chip with three overlapping SMD pads for the powerpad, but this causes a DRC clearance error. As a check, I looked at powerpad chips in the default TI Eagle library and those chips give the same error.
I’ve tried renaming all three pads to the same name, but that isn’t allowed, and I don’t see an option in the package editor to connect them](http://www.ti.com/lit/gpn/tps63000)
A while back I built a stepper motor driver based around the Allegro Microsystems A3984. It is in a TSSOP-24 package with a grounded thermal pad in the bottom. At the time, I wasn’t particularly well versed in Eagle so I didn’t bother trying to add a thermal pad to an existing TSSOP-24 package and took care of it when I got the board layout stage. What I did was create a small ground plane on the top layer of the board where the thermal pad would contact and a much larger ground plane on the opposite side to give an adequate thermal mass for cooling. I then placed several via’s between the two layers to connect them with the least thermal resistance possible. I also put a region in the t_stop layer around the top ground plane so there would be no solder mask around it. Since I was not reflowing the boards, the via’s allowed me to solder the thermal pad from the opposite side of the board.
I’m sure someone will chime in with a better way of doing it but this worked for me and only took a few minutes to implement.
Thanks, that sounds like a solution. Did you include the t_stop layer as part of the package, or was it added in at the layout stage?
I was thinking of soldering the chip the same way, adding the vias when doing the layout.
I think I’ll try using a polygon to draw the pad later, see if that works. I also just thought of trying to put in a large rectangular pad in for the powerpad, with a t_stop layer in the needed shape, but I realised that the t_stop for a pad is generated from the pad and I don’t think it can be edited seperately.
Or a combination, a smaller pad enclosed by a polygon. That might work for when a pad is absolutely needed there as part of the package.
Oh, and I should have been a bit more clear in my first post above. I’m using Eagle.
Lucien:
Thanks, that sounds like a solution. Did you include the t_stop layer as part of the package, or was it added in at the layout stage?
I did it during the board layout so I wouldn’t have to keep modifying the package should my layouts change. Now that I’m more familiar with Eagle I would probably try to integrate all into a package but back when I was originally designing my motor controller board I did what I knew would work.
Small update, I’ve tried the combination polygon and pad thing, but the dimentions are so small it’s hard to distinguish between polygon and pad. Looks like I’ll simply put in a SMD pad that fits in the required space, and place a tstop layer as required by the land pattern. Of course this means having to remember to add in the necessary copper areas when doing the layout…
But if anyone has a better idea, please do post it!
leon_heller:
Use Pulsonix! It can create pads having any shape. It cost more than Eagle, though.
No kidding… I think all the projects I have lined up combined won’t be costing me that much!
Bill, how did you place the vias on the board? I’m assuming you meant underneath the chip’s thermal pad, which is what I intended to do. The problem is Eagle’s DRC then complains of clearance errors because the via and chip overlap. I guess there’s a way of turning that off, but then the problem would be clearing the BatchPCB DRC.
All I did was use the “via” command and associate them with the GND layer. Since the polygon directly under the thermal pad was GND, the vias linked in with no problem. I also turned “thermals” off so the maximum amount of metal was touching each via.
I never ran into any DRC problems in Eagle with that board. What error is Eagle spitting back at you?
It’s giving me a clearance error. But from what you’ve just said, I suspect this is because where you have a polygon added at the layout stage, I have a SMD pad there as part of the package. So a via/SMD pad clearance error. Will have to check that.
I’m surprised you don’t get a via/component clearance issue. Guess that’s not automatic and needs some sort of keepout defined for the package.
It passes the BatchPCB bot with no issues. When laying out the board I usually autoroute first to get a basic layout idea and then rip-up and manually route each signal. In this case, I drew the ground polygon first and put a keep-out zone over it before autorouting.
