I’ve submitted a design which passed the BatchPCB DRC bot check. However the images which the bot attached to the confirmation email didn’t look as expected and had me go over the gerber files once more. The gerbers look fine in both Viewmate and GC-Prevue, however they look wrong in Gerbv and in the BatchPCB DRC bot images.
Below are screenshots from Viewmateand GC-Prevue - both of these look correct:
Below are screenshots from Gerbvand one of the images from the BatchPCB DRC-bot confirmation email. Notice that most of the pads on the rightmost IC and the connecting tracks are missing :?
I’ve submitted a design which passed the BatchPCB DRC bot check. However the images which the bot attached to the confirmation email didn’t look as expected and had me go over the gerber files once more. The gerbers look fine in both Viewmate and GC-Prevue, however they look wrong in Gerbv and in the BatchPCB DRC bot images.
Greetings Nikolaj,
I would not fab the PCB unless the BatchPCB images look correct.
What tool did you use to create the design?
Also, did you flood the ground plane after the design was routed? Can you turn the ground plane flood off and submit the project again?
Can’t comment as to your question - but I’m a bit worried about your layout. Specifically, it looks like you’re routing a trace underneath a QFN chip, between the outer pads and the center ground pad. Don’t you think this is rather dangerous? For one, I’m not sure if there actually is enough space for you to do that. I don’t think I’ve ever seen a QFN that gave enough space for you to route a trace like that. Secondly, with the solder mask on top of that trace, it’ll stick up above the pads, so I think you may have trouble soldering the part. Lastly - you don’t have that pad connected to anything. Most chips call for those pads to be grounded. I can’t recall ever seeing a chip that didn’t.
Would be interested to hear other people’s thoughts on the matter.
Also, did you flood the ground plane after the design was routed?
Yes I created the polygon plane (which connects to GND) after I had routed all other connections but GND.
Can you turn the ground plane flood off and submit the project again?
Yes I had planned that as my next step - to remove the plane and manually route the GND connections.
I’m just curious as to whether this is an error in the DRC bot or in my Gerbers. I went through some old posts and apparently other users have experienced problems with the DRC-bot and polygon pours.
NleahciM:
Can’t comment as to your question - but I’m a bit worried about your layout. Specifically, it looks like you’re routing a trace underneath a QFN chip, between the outer pads and the center ground pad. Don’t you think this is rather dangerous? For one, I’m not sure if there actually is enough space for you to do that. I don’t think I’ve ever seen a QFN that gave enough space for you to route a trace like that. Secondly, with the solder mask on top of that trace, it’ll stick up above the pads, so I think you may have trouble soldering the part. Lastly - you don’t have that pad connected to anything. Most chips call for those pads to be grounded. I can’t recall ever seeing a chip that didn’t.
Hi NleahciM,
Thanks for your input. You might very well be right in your comments - I’ve never tried laying out a QFN before, so maybe I should give that part of my design a bit more thought. Especially I didn’t consider the solder mask issue - I can definitely see that as a problem.
NleahciM:
Can’t comment as to your question - but I’m a bit worried about your layout. Specifically, it looks like you’re routing a trace underneath a QFN chip, between the outer pads and the center ground pad. Don’t you think this is rather dangerous? For one, I’m not sure if there actually is enough space for you to do that. I don’t think I’ve ever seen a QFN that gave enough space for you to route a trace like that. Secondly, with the solder mask on top of that trace, it’ll stick up above the pads, so I think you may have trouble soldering the part. Lastly - you don’t have that pad connected to anything. Most chips call for those pads to be grounded. I can’t recall ever seeing a chip that didn’t.
Would be interested to hear other people’s thoughts on the matter.
Greetings NleachciM,
I don’t share your view that routing traces (or vias) under the body of the part is a problem. Perhaps I missed something in your post?
What do you think of my this design? Here’s a fragment with an ATMEL Mega8 in the 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP).
The power and ground pins on this part are not well suited for layout on a two layer board, and so I have traces and vias under the IC body. I had issues with the first FAB of this board for noise resetting the AVR uC.
I’ve added two capacitors (C6, C8) on the bottom side for decoupling the supply (I may not install both or either one - but to be safe these are place holders - they worked to solve the problem on the first PCB design).
I’m ready to FAB the new layout shown here, which has both traces and vias under the IC body.
The power and ground pins on this part are not well suited for layout on a two layer board, and so I have traces and vias under the IC body. I had issues with the first FAB of this board for noise resetting the AVR uC.
I’ve added two capacitors (C6, C8) on the bottom side for decoupling the supply (I may not install both or either one - but to be safe these are place holders - they worked to solve the problem on the first PCB design).
I’m ready to FAB the new layout shown here, which has both traces and vias under the IC body.
Comments Welcome![/quote]
Hi Peter - I think I was not specific enough in my comments. Though I think it’s often OK to run traces beneath a package such as a TQFP, Nikolaj is using a QFN. QFNs have a ground pad in the center of the bottom of the chip, typically used (at least in my experience), for power dissipation. I hate the things. They’re a pain to desolder, and I’ve never found a way to run traces beneath them. I’m looking at the package layout for the ATMEGA168 in the MLF/QFN package, and they show .2mm between the outer pads and the center ground pad. You can’t get much of a trace in between that! That is fairly typical, too. Thus I suspect Nikolaj did not draw the ground pad big enough and that the ground pad on his PCB will be sitting directly on top of that one trace. Not good! Especially considering the quality of Gold Phoenix boards (again - not good!), he is playing with fire, unless he’s using a very oddly proportioned QFN.
NleahciM:
Hi Peter - I think I was not specific enough in my comments. Though I think it’s often OK to run traces beneath a package such as a TQFP, Nikolaj is using a QFN.
NleahciM:
You can’t get much of a trace in between that! That is fairly typical, too. Thus I suspect Nikolaj did not draw the ground pad big enough and that the ground pad on his PCB will be sitting directly on top of that one trace. Not good! Especially considering the quality of Gold Phoenix boards (again - not good!), he is playing with fire, unless he’s using a very oddly proportioned QFN.
Mike,
Thanks for the clarification - my error regarding QFNs. So, does this mean that the metal tab under the QFN is soldered down?
If so, would it not be wise to place many vias and a similar pad on the bottom layer? This way a hot iron can be used on the botton layer to unsolder the centre pad.
Thanks for the clarification - my error regarding QFNs. So, does this mean that the metal tab under the QFN is soldered down?
If so, would it not be wise to place many vias and a similar pad on the bottom layer? This way a hot iron can be used on the botton layer to unsolder the centre pad.
Comments Welcome!
Peter - in my experience, the bottom pad on a QFN is always soldered down. I have yet to see one that is not supposed to be, though it is possible that they exist.
The first time I had to solder a chip with a package like this I designed the PCB very similarly to what you describe, except that I made just one large via, just large enough for me to sneak my finest iron tip up right to the bottom of the chip. This seemed to work OK, though it seemed as if the via was causing the rest of the chip to sit just slightly above the rest of the pads, as if the via was sticking up just a tenth of a millimeter or something. I’m not positive that that was the case, but it seemed to be. I did try once to remove one of these parts, and was entirely not successful. I suspect if I had cared less about the chip (they were about $25 each!) I would have been more willing to just let my iron sit on it and heat it up, but I was a bit nervous and after a while I gave up.
The most recent QFN that I’ve had to solder I went for the route of putting paste on the center pad, then soldering the outer pads, and then heating up the whole board with a hot air tool. I found this to be an easier process. I didn’t use a via to the bottom on that most recent one.
NleahciM:
QFNs have a ground pad in the center of the bottom of the chip, typically used (at least in my experience), for power dissipation.
Since the IC draws a max of 1mA peak, I didn't believe that thermal relief was needed here. However looking at the datasheet again it actually says that the thermal pad should be connected to GND.
NleahciM:
Thus I suspect Nikolaj did not draw the ground pad big enough and that the ground pad on his PCB will be sitting directly on top of that one trace.
That's true, and as I wrote before I see the problem here.
Note again - I have not added solder to the center pad. This is a common misconception and problem. Almost all center pads are ground connections in addition to ground connections on exterior pads (so you don’t even need the center pad connection). Soldering of the center pad is very rarely required! Don’t even worry about it. If you do add solder to the center pad, you will need to wick it away. This is a large center pad very close to the exterior pads (bad design on my part). The center pad will very actively suck solder towards it if you get sloppy. If you’re designing your own footprint for a device, be sure to make the center pad smaller and away from exterior pads
<LINK_TEXT text=“http://www.imagewoof.com/view_thumb/d3c … ewmate.JPG”>http://www.imagewoof.com/view_thumb/d3c081434/viewmate.JPG</LINK_TEXT>
<LINK_TEXT text=“http://www.imagewoof.com/view_thumb/09d … prevue.JPG”>http://www.imagewoof.com/view_thumb/09dde1403/gcprevue.JPG</LINK_TEXT>
<LINK_TEXT text=“http://www.imagewoof.com/view_thumb/182 … drcbot.JPG”>http://www.imagewoof.com/view_thumb/1821c1405/batchpcb-drcbot.JPG</LINK_TEXT>
){kind=link}