Dear All,
I’m rather new to Eagle and I experience a problem.
I designed a four layer board inner layer one is a supply layer.
Called $AGND. The second inner layer is routed and contains
A polygon VCC that covers the entire PCB.
My problems are the following:
Inner layer one: Supply layer AGND
All pads are generated on the Gerber and no copper areas, so actually a positive of the
display in the board is generated not the promised negative. At generation of the
Gerber I deselected via’s and pads as mentioned in the CADSOFT FAQ section.
Inner layer two:
Pads of my pin headers are connected to the copper of the polygon although they
Have different signal names and in the Eagle display they have the required
Clearance.
Pad of SMD capacitors placed on the BOTTOM layer appear in this layer to
During Gerber generation the bottom layer was absolutely not selected. I checked
And double checked.
Hope someone can help me with these problems
Regards,
Jos van Hertrooij