Eagle pcb design question on vias

Community PCB Design
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I am working on a power distro board and having a little trouble placing vias around the smd pads . Essentially what i want to do is place vias around a smd pad inside a polygon . What is the best way to do this? When i try to place a polygon around the vias and smd pad (naming it gnd which is the bottom layer polygon copper pour) The polygon wont isolate from the top pwr plane .i even tried changing the rank of the polygon. If i make the polygon smaller where the vias isolation itself makes it isolated it sorta works but looks weird like the bottom pad in the pic.

I also tried placing a rectangle around the vias and pads which does isolate from the power plane but im not sure this is the correct way of doing it. i also cant name the rectangle of course. Shown in top right pad in pic

To add a little more info, both pad and all vias are named gnd .The polygon is also named gnd .The bottom of the board is the ground plane named gnd as well. The vias look ok on the bottom layer. Both ways polygon or rectangle also give me clearance and overlap drc errors on all the vias.

what is the correct way to do this ? I dont wanna send the boards out to be made and have a issue.

Heres a pic of what i mean . The bottom pad is with a polygon around it and the vias isolation you can see is whats seperating it from the top power plane. If i make the polygon bigger no matter what i try it wont seperate from the power plane. On the top right pad in the pic i used a rectangle instead of polygon and it does isolate itself from the power plane but not sure if this is correct and it still gives me drc clearence errors on every via because of the rectangle.

btw dont mind the messed up yellow silkscreen. i was just moving it around.

[<LINK_TEXT text=“http://i449.photobucket.com/albums/qq21 … adsvia.jpg”>http://i449.photobucket.com/albums/qq214/boostedrst/padsvia.jpg</LINK_TEXT>](Photo Storage)

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Ranking the polygon is what you want. I can’t remember the steps I took when I had to do it. You can Google around for a tutorial for ranks in Eagle though. The ranking system is tricky when you haven’t used them before. There is a certain procedure you have to follow to get it to work right.

If you still can’t get it, you could send me your files and I can play with it.

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codlink:
Ranking the polygon is what you want. I can’t remember the steps I took when I had to do it. You can Google around for a tutorial for ranks in Eagle though. The ranking system is tricky when you haven’t used them before. There is a certain procedure you have to follow to get it to work right.

If you still can’t get it, you could send me your files and I can play with it.

Thank you so much . That was a big help. I kinda knew it had something to do with the ranks but your post made me go play around with the ranks more and i got it . I had to set the main polygons to rank 2 and the small polygons to rank 1 . I was doing it backwards.

If you dont mind i would still like if you could check out my design and let me know if you see anything that is bad. I will pm you the dropbox link.

Another question i have is can you have a trace running through a trestrict polygon or do i have to t restrict around the traces? Lastly when i do a grid check i get a few errors on the drc however when i designed the board i never changed the grid spacing at all . im very strict about that and always leave it at 1.27mm or multiple of 1.27 like .635.Everytime i ran a trace to a pad i got the connect sound,the trace moves with the pad and all .Always alighned to the center of a pad so i dont see how it can be off grid. Is this a fluke maybe?

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Here is the updated files per the PM I sent.