Greetings:
I am experiencing interrupt detection failures with multiple LPC2103 timer IRQs assigned to different VIC channels.
With “timer0”, match register 0 interrupt assigned to IRQ0 the timer0 interrupt works as expected. When I add a second IRQ, in this case “timer3”, match register 1 to IRQ1 then the IRQ0 interrupt is no longer detected.
I have read the VIC registers and confirmed both interrupt channels are enabled and have the proper VIC channel vector addresses. I have swapped interrupt channels and found the timer0 interrupt still works by itself but stops when the timer3 IRQ is placed in this case on IRQ0.
The code execution does seem to exit the first handler OK and return to the main program but then the second pending interrupt is not detected. If I disable the “timer3” IRQ then the original timer0 interrupt again works normally. Sometimes the execution becomes trapped within the “UnDef” forever loop.
I noticed there is an outstanding GCC bug registered for “arm-elf-gcc” regarding incorrect IRQ code generation but I don’t understand GCC well enough to determine if it might apply to this case.
It would be most helpful if I could find examples of GCC code for multiple LPC2xxx VIC IRQs. I wonder if anyone in this group knows of working GCC code with multiple VIC IRQ interrupts that I could study? If so please either point me to it or post the initialization code and the associated IRQ handler routines here.
Many thanks in advance for any enlightenment!
Tom Alldread