GDB 7.5 and OpenOCD 0.6.1 "JTAG-DP STICKY ERROR" on LM3S9B90

Development Boards MicroMod
1

Hello everyone,

I’m facing a very weird problem… the “JTAG-DP STICKY ERROR”!

I’m running GDB 7.5 and OpenOCD 0.6.1 on a EK-LM3S9B90 board (ARM Cortex-M3).

Introduction

After analyzing the LM3S9B90’s data sheet to find which are the addresses of some the processor registers addresses.

-Watchdog Timer 1, Watchdog Load: 0x40000000, Read/Write

-Watchdog Timer 1, Watchdog Value: 0x40000004, Read

…

-GPIO Port A, GPIO Data: 0x40004000, Read/Write

-GPIO Port A, GPIO Direction: 0x40004400, Read/Write

…

-UART0, UART Data: 0x4000C000, Read/Write

-UART0, UART Flag: 0x4000C018, Read

Problem

What i want to do is:

Change/Get the actual value on some register, what i do is, example for “Watchdog Timer 1, Watchdog Load” register:

monitor mdw 0x40000000 #Get value
monitor mww 0x40000000 0x00000000 #Change value
monitor mdw 0x40000000 #Get value

And this commands will give a JTAG error like:

(gdb) monitor mdw 0x40000000
JTAG-DP STICKY ERROR
MEM_AP_CSW 0x23000052, MEM_AP_TAR 0x40000004
JTAG-DP STICKY ERROR
MEM_AP_CSW 0x23000052, MEM_AP_TAR 0x40000004
Block read error address 0x40000000
in procedure 'mdw'

(gdb) monitor mww 0x40000000 0x00000000
JTAG-DP STICKY ERROR
MEM_AP_CSW 0x23000052, MEM_AP_TAR 0x40000004
JTAG-DP STICKY ERROR
MEM_AP_CSW 0x23000052, MEM_AP_TAR 0x40000004

(gdb) monitor mdw 0x40000000
JTAG-DP STICKY ERROR
MEM_AP_CSW 0x23000052, MEM_AP_TAR 0x40000004
JTAG-DP STICKY ERROR
MEM_AP_CSW 0x23000052, MEM_AP_TAR 0x40000004
Block read error address 0x40000000
in procedure 'mdw'

In some forums i saw that this problem can be related to the ```
adapter_khz 500


<U>[u]<B>**"funny thing"**</B>[/u]</U>

Some of the registers work perfectly, like:

GPIO Port A, GPIO Port B, GPIO Port D, UART0, USB, HIBERNATION Module, Flash memory control, System Control.

Can see the full list on this url: [https://dl.dropboxusercontent.com/u/134 ... isters.pdf](https://dl.dropboxusercontent.com/u/13427263/registers.pdf)

<U>[u]<B>**FYI**</B>[/u]</U>

To connect to the LM3S9B90 i'm using the default configuration (ek-lm3s9b9x.cfg):

C:/openocd-bin/openocd.exe" -f "C:/openocd-bin/board/ek-lm3s9b9x.cfg

With the GDB 7.5:

target remote | “C:/openocd-bin/openocd.exe” --pipe -f “C:/openocd-bin/board/ek-lm3s9b9x.cfg”


Please Help me.. if you need more info.. just ask ;)
2

Hi joaomqcunha,

I am not familiar with the LM3S9B90 but did you followed the sequenz on the Datasheet to use the WDT

To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register,
see page 267.

I can Imagine if you do not do this the WDT is in a powersaving mode. But because I am a beginner: without engagement :wink:

Cheers

MaTT

— Update —

WDT1 Clock Gating Control:

This bit controls the clock gating for the Watchdog Timer module 1. If

set, the module receives a clock and functions. Otherwise, the module

is unclocked and disabled. If the module is unclocked, a read or write

to the module generates a bus fault.

Run Mode Clock Gating Control Register 0 (RCGC0)

Base 0x400F.E000

Offset 0x100

Type R/W, reset 0x00000040

28 WDT1

3

What you are saying is to add this lines to my openocd .cfg file?

set SYSCTL_RCGC0 0x400FE100
mww $SYSCTL_RCGC0 0x00000040

Already done that and it gives me the same error :frowning:

4

joaomqcunha,

Please read the datasheet, the reset value of that register is 0x00000040 which means only bit 7 is set (enabled).

So to enable watchdog 1 we need to set bit 28, eg

mww 0x400FE100 0x10000040

if you also wanted watchdog 0 enabled then you would set bit 3.

Spen

5

I understand now… it works!!!

Thanks to niedermaier and ntfreak for your replies :smiley: