When I debug the CMSIS routine SystemInit() thinks the processor is set to 72MHz, but it is running at 60MHz. Once I disconnect the JTAG and cycle the power then it runs at 72MHz. Does anyone know who is controlling the clock speed (and how) during JTAG?
Coincidentally the difference happens to be one increment of SYSPLLCTRL, where frequency is (SYSPLLCTRL +1 ) * CLK.
I tried changing SYSPLLCTRL to 4 (from 5) same behaviour at a slower clock speed. It still seems to be off by 1 step of SYSPLLCTRL.
I am using IAR-EW-ARM as the IDE/Toolchain. I upgraded to the latest version 6.1
The JTAG device is Olimex ARM-JTAG-EW. I upgraded (with new firmware and DLL) to 1.06.
Neither upgrade affected any change of behaviour.
Any ideas?