Newbie PLL questions

Development Boards MicroMod
1

Colleagues,

According to the “Insider guide”, the PLL accepts input clock

frequencies between 10MHz and 25MHz. The development board schematics

out there use 10MHz or 12 MHz crystals.

I tend to use 7.3278MHz or 29.4912MHz oscillators (because they can be

easily divided into some of “sweet spot” frequencies used in the other

parts of the circuit). Unfortunately, first one is too slow and the

second one is too fast for the PLL. Power and EMI are usually not a

problem for me.

So, I have two questions:

  • What happens if the PLL gets a clock input below the 10-25MHz range?

  • Is there a way to bypass the PLL and feed the 29.4912MHz directly to

the CPU?

Cheers!

  • Nick
2

Why not use a 10/12 MHz crystal like everyone else? The chips have a fractional baud-rate generator which gives negligible errors.

Leon

3

leon_heller:
Why not use a 10/12 MHz crystal like everyone else? The chips have a fractional baud-rate generator which gives negligible errors.

Leon

Leon,

I think I’ve preemptively answered your question in my original post. The “sweet spot” frequencies that I was talking about are not the baud rates. I’m not new to embedded design, just new to LPC2000. I’m aware of some of the alternatives, however I’m trying to build understanding of the components I’ll be working with.

So, the original questions remain.

  • Nick
4

kender:
According to the “Insider guide”, the PLL accepts input clock frequencies between 10MHz and 25MHz. The development board schematics out there use 10MHz or 12 MHz crystals.

I tend to use 7.3278MHz or 29.4912MHz oscillators (because they can be easily divided into some of “sweet spot” frequencies used in the other parts of the circuit).

My Embedded Artists board uses a 14.7456 Mhz crystal - maybe that frequency (being exactly half) would suit you better?

So, I have two questions:

  • What happens if the PLL gets a clock input below the 10-25MHz range?

  • Is there a way to bypass the PLL and feed the 29.4912MHz directly to

the CPU?

I don't know but you may be able to answer the questions yourself after reading the NXP Application note AN10331 which describes the PLL operation in detail:

http://www.nxp.com/acrobat_download/app … 0331_1.pdf

5

cfb:

kender:
So, I have two questions:

  • What happens if the PLL gets a clock input below the 10-25MHz range?

  • Is there a way to bypass the PLL and feed the 29.4912MHz directly to

the CPU?

I don't know but you may be able to answer the questions yourself after reading the NXP Application note AN10331 which describes the PLL operation in detail:

http://www.nxp.com/acrobat_download/app … 0331_1.pdf

Thanks for the reference to the app note. It seems from Fig.1 and Table 1 that the PLL can be bypassed, if I set the PLCC and/or PLLE low. I’ll try that and I’ll keep this thread updated.