openocd 0.1.0 halt after reset

Development Boards MicroMod
1

I’m using Openocd 0.1.0 on Windows with an STM32F103. Mostly works great.

However, after issuing a reset command, the target runs for around 300mS and stops with the following error:

target state: halted

target halted due to undefined, current mode: Thread

The same target does not halt during a normal reset or power on reset.

Issuing a resume command after the halt does restart the processor.

From the command link:

openocd -f stm32_ocd.cfg

From telnet localhost 4444:

Open On-Chip Debugger

reset

JTAG tap: stm32.cpu tap/device found: 0x3ba00477 (Manufacturer: 0x23b, Part: 0xba00, Version: 0x3)

JTAG Tap/device matched

JTAG tap: stm32.bs tap/device found: 0x06414041 (Manufacturer: 0x020, Part: 0x6414, Version: 0x0)

JTAG Tap/device matched

target state: halted

target halted due to undefined, current mode: Thread

xPSR: 0x61000000 pc: 0x080040a6

The following is the stm32_ocd.cfg file.

gdb_port 3333
telnet_port 4444
tcl_port 6666

interface ft2232
ft2232_device_desc "usbScarab A"
ft2232_layout olimex-jtag

jtag_khz 500
jtag_nsrst_delay 100
jtag_ntrst_delay 100

reset_config trst_and_srst separate 

jtag newtap stm32 cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x3ba00477
jtag newtap stm32 bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id 0x06414041

target create stm32.cpu cortex_m3 -endian little -chain-position 0

stm32.cpu configure -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0

flash bank stm32x 0x08000000 0x20000 0 0 0 

init

How do I get it to run without halting after reset.

Thanks

2

Try resetting with reset run, since reset alone defaults to reset halt.

3

I’m having this same problem.

I’ve narrowed it down (I think) to a multiple bugs in cortex_m3.c. I’ll write up what I think is happening and send it to the list in a day or two. I didn’t read the code enough to grok the whole thing but here’s what I think is going on.

bug 1) cortex_m3_assert_reset() called cortex_m3_clear_halt(), which contrary to its name, doesn’t clear the halt flag, but instead sets C_HALT.

bug 2) cortex_m3_poll() does an atomic read on DCB_DHCSR, checks if the target is resetting, and then calls cortex_m3_endreset_event(), which should reset the DHCSR to its reset state. Unfortunately, the atomic read which checks that state is called before endreset_event(), so when it checks (dcb_dhcsr & S_HALT), it’s using the old value of DHCSR, then halts the target, leaving you right back where you started (halted).

Making assert_reset() actually clear C_HALT and adding another read in poll() fixed the problem for me.

4

To the previous post, I did try reset run as well. According to the manual, a reset with a parameter is the same as reset run.

Looks like you are narrowing it down. The same code works with the LPC2148 family of ARM processors. (With changes to the JTAG details of course). It runs without halting.

I’ve been using the precompiled Open OCD 0.1.0 Windows installer. I’m sure I could get the SVN code to compile, but at some point you have to do real work, rather than build tool sets.

Thanks for all your effort. Let me know if there is anything i can do to help.

5

Here’s a diff for cortex_m3.c

I have no idea if this is even a bug or if I this is completely wrong since I can’t seem to get a hold of any openocd devs, but it seems to solve the problem for me, so it might help you.

Index: cortex_m3.c
===================================================================
--- cortex_m3.c	(revision 1411)
+++ cortex_m3.c	(working copy)
@@ -444,6 +444,7 @@
 		prev_target_state = TARGET_RUNNING;
 	}
 	
+    ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 	if (cortex_m3->dcb_dhcsr & S_HALT)
 	{
 		target->state = TARGET_HALTED;
@@ -725,8 +726,9 @@
 		if (cortex_m3->dcb_dhcsr & C_MASKINTS)
 			ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT);
 	
-		cortex_m3_clear_halt(target);
-							
+        /* Clear C_HALT  */
+        ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+
 		/* Enter debug state on reset, cf. end_reset_event() */	
 		ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
 	}
6

Strong work! That corrected the problem. Building openocd wasn’t too painful. The “How to build OpenOCD for windows” Sticky posting has good instructions.

Having the Windows installer is nice. Does anyone know if the patch will get applied and the installer updated?