I am trying to use the program command in openocd-0.7.0 which seems simple enough to use.
I have programmed the board using ISP using a hex file and “FlashMagic” with no problems
It seems the first section of memory interrupt vectors up to 0x3f is being programmed with
some other information.
Is there any reason why this would occur?
I created a config file for lpc2134 as follows
# NXP LPC2134 ARM7TDMI-S with 128kB flash and 16kB SRAM, clocked with 14.7456MHz crystal
source [find target/lpc2xxx.cfg]
# parameters:
# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
proc setup_lpc2134 {core_freq_khz adapter_freq_khz} {
# 256kB flash and 16kB SRAM
# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
setup_lpc2xxx lpc2134 0x4f1f0f0f 0x20000 lpc2000_v2 0x4000 $core_freq_khz $adapter_freq_khz
}
proc init_targets {} {
# default to core clocked with 14.7456MHz crystal
echo "Warning - assuming default core clock 14.7456MHz! Flashing may fail if actual core clock is different."
# setup_lpc2134 <core_freq_khz> <adapter_freq_khz>
setup_lpc2134 147456 250
}
here is the transcript:
c:\openocd-0.7.0\bin>openocd-0.7.0.exe -f …/scripts/interface/olimex-arm-usb-oc
d.cfg -f …/scripts/board/adm.cfg -c “program adm.hex verify reset”
Open On-Chip Debugger 0.7.0 (2013-05-05-10:41)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.sourceforge.net/doc/doxygen/bugs.html
Info : only one transport option; autoselect ‘jtag’
init_targets
Warning - assuming default core clock 14.7456MHz! Flashing may fail if actual co
re clock is different.
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain connect_de
assert_srst
adapter_nsrst_delay: 100
jtag_ntrst_delay: 100
adapter speed: 250 kHz
Info : clock speed 250 kHz
Error: JTAG scan chain interrogation failed: all ones
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway…
Error: lpc2134.cpu: IR capture error; saw 0x0f not 0x01
Warn : Bypassing JTAG setup events due to errors
Info : Embedded ICE version 15
Error: unknown EmbeddedICE version (comms ctrl: 0xffffffff)
Info : lpc2134.cpu: hardware has 2 breakpoint/watchpoint units
Warn : ThumbEE – incomplete support
Error: JTAG scan chain interrogation failed: all ones
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway…
Error: lpc2134.cpu: IR capture error; saw 0x0f not 0x01
Warn : Bypassing JTAG setup events due to errors
Warn : ThumbEE – incomplete support
target state: halted
target halted in ThumbEE state due to debug-request, current mode: System
cpsr: 0xffffffff pc: 0xfffffff9
Warn : NOTE! DCC downloads have not been enabled, defaulting to slow memory writ
es. Type ‘help dcc’.
Warn : NOTE! Severe performance degradation without fast memory access enabled.
Type ‘help fast’.
** Programming Started **
auto erase enabled
Info : Padding image section 0 with 11564 bytes
Warn : ThumbEE – incomplete support
Warn : target reentered debug state, but not at the desired exit point: 0xffffff
f9
Warn : lpc2000 prepare sectors returned 150
Error: failed erasing sectors 0 to 8
** Programming Failed **
shutdown command invoked
c:\openocd-0.7.0\bin>openocd-0.7.0.exe -f …/scripts/interface/olimex-arm-usb-oc
d.cfg -f …/scripts/board/adm.cfg -c “program adm.hex verify reset”
Open On-Chip Debugger 0.7.0 (2013-05-05-10:41)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.sourceforge.net/doc/doxygen/bugs.html
Info : only one transport option; autoselect ‘jtag’
init_targets
Warning - assuming default core clock 14.7456MHz! Flashing may fail if actual co
re clock is different.
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain connect_de
assert_srst
adapter_nsrst_delay: 100
jtag_ntrst_delay: 100
adapter speed: 250 kHz
Info : clock speed 250 kHz
Info : JTAG tap: lpc2134.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf
1f0, ver: 0x4)
Info : Embedded ICE version 4
Info : lpc2134.cpu: hardware has 2 breakpoint/watchpoint units
Info : JTAG tap: lpc2134.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf
1f0, ver: 0x4)
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
Warn : NOTE! DCC downloads have not been enabled, defaulting to slow memory writ
es. Type ‘help dcc’.
Warn : NOTE! Severe performance degradation without fast memory access enabled.
Type ‘help fast’.
** Programming Started **
auto erase enabled
Info : Padding image section 0 with 11564 bytes
Warn : Verification will fail since checksum in image (0xe1a00000) to be written
to flash is different from calculated vector checksum (0xb9205f80).
Warn : To remove this warning modify build tools on developer PC to inject corre
ct LPC vector checksum.
wrote 65536 bytes from file adm.hex in 12.505715s (5.118 KiB/s)
** Programming Finished **
** Verify Started **
Error: checksum mismatch - attempting binary compare
diff 0 address 0x00000000. Was 0x34 instead of 0x18
diff 1 address 0x00000001. Was 0x40 instead of 0xf0
diff 2 address 0x00000004. Was 0x02 instead of 0x18
diff 3 address 0x00000005. Was 0x50 instead of 0xf0
diff 4 address 0x00000006. Was 0xa0 instead of 0x9f
diff 5 address 0x00000007. Was 0xe3 instead of 0xe5
diff 6 address 0x00000008. Was 0x00 instead of 0x18
diff 7 address 0x00000009. Was 0x50 instead of 0xf0
diff 8 address 0x0000000a. Was 0x84 instead of 0x9f
diff 9 address 0x0000000c. Was 0x03 instead of 0x18
diff 10 address 0x0000000d. Was 0x50 instead of 0xf0
diff 11 address 0x0000000e. Was 0xa0 instead of 0x9f
diff 12 address 0x0000000f. Was 0xe3 instead of 0xe5
diff 13 address 0x00000010. Was 0x04 instead of 0x18
diff 14 address 0x00000011. Was 0x50 instead of 0xf0
diff 15 address 0x00000012. Was 0x84 instead of 0x9f
diff 16 address 0x00000014. Was 0x1c instead of 0x00
diff 17 address 0x00000015. Was 0x20 instead of 0x00
diff 18 address 0x00000016. Was 0x9f instead of 0xa0
diff 19 address 0x00000017. Was 0xe5 instead of 0xe1
diff 20 address 0x00000018. Was 0x00 instead of 0xf0
diff 21 address 0x00000019. Was 0x30 instead of 0xff
diff 22 address 0x0000001a. Was 0xa0 instead of 0x1f
diff 23 address 0x0000001b. Was 0xe3 instead of 0xe5
diff 24 address 0x0000001c. Was 0x93 instead of 0x18
diff 25 address 0x0000001d. Was 0x00 instead of 0xf0
diff 26 address 0x0000001e. Was 0x02 instead of 0x9f
diff 27 address 0x0000001f. Was 0xe1 instead of 0xe5
diff 28 address 0x00000020. Was 0x28 instead of 0x58
diff 29 address 0x00000021. Was 0x20 instead of 0x00
diff 30 address 0x00000022. Was 0x82 instead of 0x00
diff 31 address 0x00000023. Was 0xe2 instead of 0x00
diff 32 address 0x00000024. Was 0x93 instead of 0x40
diff 33 address 0x00000025. Was 0x10 instead of 0x00
diff 34 address 0x00000026. Was 0x02 instead of 0x00
diff 35 address 0x00000027. Was 0xe1 instead of 0x00
diff 36 address 0x00000028. Was 0x07 instead of 0x44
diff 37 address 0x00000029. Was 0x30 instead of 0x00
diff 38 address 0x0000002a. Was 0xc0 instead of 0x00
diff 39 address 0x0000002b. Was 0xe3 instead of 0x00
diff 40 address 0x0000002c. Was 0x28 instead of 0x48
diff 41 address 0x0000002d. Was 0x30 instead of 0x00
diff 42 address 0x0000002e. Was 0x02 instead of 0x00
diff 43 address 0x0000002f. Was 0xe5 instead of 0x00
diff 44 address 0x00000030. Was 0x04 instead of 0x4c
diff 45 address 0x00000031. Was 0xf0 instead of 0x00
diff 46 address 0x00000032. Was 0x1f instead of 0x00
diff 47 address 0x00000033. Was 0xe5 instead of 0x00
diff 48 address 0x00000034. Was 0xc4 instead of 0x00
diff 49 address 0x00000035. Was 0xd1 instead of 0x00
diff 50 address 0x00000036. Was 0xff instead of 0x00
diff 51 address 0x00000037. Was 0x7f instead of 0x00
diff 52 address 0x00000038. Was 0x14 instead of 0x50
diff 53 address 0x00000039. Was 0xc0 instead of 0x00
diff 54 address 0x0000003a. Was 0x02 instead of 0x00
diff 55 address 0x0000003b. Was 0xe0 instead of 0x00
diff 56 address 0x0000003c. Was 0x00 instead of 0x54
diff 57 address 0x0000003d. Was 0xc0 instead of 0x00
diff 58 address 0x0000003e. Was 0x1f instead of 0x00
diff 59 address 0x0000003f. Was 0xe0 instead of 0x00
No more differences found.
** Verify Failed **
** Resetting Target **
Error: JTAG scan chain interrogation failed: all ones
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway…
Error: lpc2134.cpu: IR capture error; saw 0x0f not 0x01
Warn : Bypassing JTAG setup events due to errors
Warn : ThumbEE – incomplete support
target state: halted
target halted in ThumbEE state due to watchpoint, current mode: System
cpsr: 0xffffffff pc: 0xfffffff9
Warn : NOTE! DCC downloads have not been enabled, defaulting to slow memory writ
es. Type ‘help dcc’.
Warn : NOTE! Severe performance degradation without fast memory access enabled.
Type ‘help fast’.
shutdown command invoked