I’m using now SAM_I_AM and freesba as SAM-BA monitor/client on my computer (host) . every time I erase my chip using ERASE pin and reflash SAM-BA bootloader using TST pin , monitor successes and communicate with SAM-BA , but most of time when I replug the usb cable it fails to communicate , and I need to reflash SAM-BA again . some times while the same session it fails .
any help ?!
P.S: my old topic would help :
http://www.at91.com/forum/viewtopic.php/f,15/t,21642/
and I had lots of info of my chip( crystal - usb - registers …) I get them when I communicate using SAM_I_AM ans freesba programs , but they need an expert (not a beginner like me 
) to understand what happed :
Bus 004 Device 023: ID 03eb:6124 Atmel Corp. at91sam SAMBA bootloader
--------------freesba monitor------------------
yahya@Notebook-PC:~$ freesba -i /dev/ttyACM0 -b 115200
Type ‘help’ to view list of supported commands
or ‘help ’ to view command’s help
SAM-BA> open
SAM-BA> info
Port: /dev/ttyACM0 opened.
Baud: 115200.
Protocol: RAW
SAM-BA> show id
Identification
CIDR = 0x270C0740
Version: 0
Processor: ARM7TDMI
NVP Type: Embedded Flash
NVP Size: 128K
NVP2 Size: None
SRAM Size: 128K
Architecture: AT91SAM7Sxx
Extended CIDR no
AT91SAM7S128 detected.
Flash page size used: 256
SAM-BA> show id
Identification
CIDR = 0x270C0740
Version: 0
Processor: ARM7TDMI
NVP Type: Embedded Flash
NVP Size: 128K
NVP2 Size: None
SRAM Size: 128K
Architecture: AT91SAM7Sxx
Extended CIDR no
AT91SAM7S128 detected.
Flash page size used: 256
SAM-BA> help show
Usage:
show [id | efc]
Show various parameters.
id - Show CID register.
efc - Show Embedded Flash Controller Status.
SAM-BA> show efc
Embedded Flash Controller (EFC)
FMR = 0x00340100
Flash Status: BUSY
Errors: PROGE: 0 LOCKE: 0
Erase Before Programming: YES
Flash Wait State:
Read: 2 cycles
Write: 3 cycles
Flash Microsecond Cycle Number: 52
FSR = 0x00030001
Flash Status: READY
Errors: PROGE: 0 LOCKE: 0
Security bit: Inactive
General-purpose NVM
GPNVM0: 0 BOD: Disabled
GPNVM1: 0 BOD Reset: Disabled
GPNVM2: 0 Memory: Flash/SRAM
LOCKS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SAM-BA> show id
Identification
CIDR = 0x270C0740
Version: 0
Processor: ARM7TDMI
NVP Type: Embedded Flash
NVP Size: 128K
NVP2 Size: None
SRAM Size: 128K
Architecture: AT91SAM7Sxx
Extended CIDR no
AT91SAM7S128 detected.
Flash page size used: 256
SAM-BA> help read
Usage:
read
Read a word from the given address. The address must be word-aligned.
SAM-BA> read 2000
0x00490849
SAM-BA> open
SAM-BA> info
Port: /dev/ttyACM1 opened.
Baud: 115200.
Protocol: RAW
SAM-BA> flash 0x00100000 AT91SAM7_P64_blinking_led.BIN
Detecting microcontroller: 0x270C0740
Version: 0
Processor: ARM7TDMI
NVP Type: Embedded Flash
NVP Size: 128K
NVP2 Size: None
SRAM Size: 128K
Architecture: AT91SAM7Sxx
Extended CIDR no
AT91SAM7S128 detected.
Loading sambaflash
Sending data to RAM using RAW protocol with block size 128 bytes.
Bytes: 1720, Blocks: 14
Sending Block 14 / 14 Finished
Programming Flash with page size 256
Bytes: 688, Pages: 3
Programming page 3 / 3
Finished
--------------SAM_I_AM monitor------------------
info usb
UDP_GLB_STAT: 00000002
Device in address state: false
Device configured: true
Send resume enabled: false
Resume sent to host: false
Remote wake-up enable: false
UDP_FADDR: 0000011B
Function address: 27 Function enabled: true
UDP_IMR: 00001200
Interrupts enabled:
Endpoint 0: false Endpoint 1: false Endpoint 2: false Endpoint 3: false
Suspend: false Resume: true External resume: false Start-of-frame: false
Bus wakeup: false
Endpoint 0 (UDP_CSR0: 00088000)
Enabled: true Endpoint type: control
Data IN ACK: false Data in bank 0: false Data in bank 1: false
Received data count: 8
Setup packet available: false Stall acknowledged: false
Transmitter ready: false
Transfer direction: OUT
Endpoint 1 (UDP_CSR1: 00008A00)
Enabled: true Endpoint type: bulk OUT
Data IN ACK: false Data in bank 0: false Data in bank 1: false
Received data count: 0
Stall acknowledged: false
Transmitter ready: false
Endpoint 2 (UDP_CSR2: 00008600)
Enabled: true Endpoint type: bulk IN
Data IN ACK: false Data in bank 0: false Data in bank 1: false
Received data count: 0
Stall acknowledged: false
Transmitter ready: false
Endpoint 3 (UDP_CSR3: 00008500)
Enabled: true Endpoint type: isochronous IN
Data IN ACK: false Data in bank 0: false Data in bank 1: false
Received data count: 0
CRC error: false
Transmitter ready: false
PMC_SCSR: 00000081
Processor clock: ENABLED USB clock: ENABLED
Programmable clocks: 0: disabled 1: disabled 2: disabled
PMC_PCSR: 00000800
Peripheral clocks:
AICFIQ: disabled SYSIRQ: disabled PIOA: disabled ADC: disabled
SPI: disabled USART0: disabled USART1: disabled SSC: disabled
TWI: disabled PWMC: disabled UDP: ENABLED TC0: disabled
TC1: disabled TC2: disabled AICIRQ0: disabled AICIRQ1: disabled
CKGR_MOR: 00004001
Main oscillator: ENABLED Oscillator bypass: disabled
Oscillator startup: 64 slow clock cycles
CKGR_MCFR: 000127BE
Clock cycles in 16 slow clock periods: 10174
Slow clock is 28.987 kHz if main clock is 18.432 MHz
Main clock ready: true
CKGR_PLLR: 10483F0E
PLL DIV: 14 MUL: 72 USBDIV: 1 OUT: 0
PLL frequency: 96.110 MHz (assuming 18.432 MHz oscillator)
USB frequency: 48.055 MHz
PMC_MCKR: 00000001
Master clock: main clock Prescale: divide-by-1
Device is operating at 18.4 MHz
PMC_PCK0: 00000000 PMC_PCK1: 00000000 PMC_PCK2: 00000000
Programmable clock 0: slow clock Prescale: divide-by-1
Programmable clock 1: slow clock Prescale: divide-by-1
Programmable clock 2: slow clock Prescale: divide-by-1
PMC_SR: 0000000D
Main oscillator stable: true PLL locked: true Master clock ready: true
Programmable clocks ready: 0: false 1: false 2: false
PMC_SR: 0000000D
Main oscillator stable: true PLL locked: true Master clock ready: true
Programmable clocks ready: 0: false 1: false 2: false
PMC_IMR: 00000000
Interrupts enabled:
Main oscillator status: false
PLL lock: false
Master clock ready: false
Programmable clock ready: 0: false 1: false 2: false
version
v1.4 Nov 10 2004 14:49:33