In doing the post-mortem / rev-b of my first board, I was trying to figure out why none of my solder side silkscreen was printed. The SFE PCB service lists two sided silkscreen and I have seen pictures of another board with it. After looking though the EAGLE manual and CAM processor, it appears the job step needed to produce the .pls file is missing from SFE-Special. I was able to modify SFE-Special to produce the .pls file with the following steps:
1-Open the SFE-Special CAM job
2-Click the Silk Screen CMP tab
3-Click the Add button
4-Change section name to Silk Screen SOL
5-Change file to .pls
6-Deselect layer 21, select layer 22
7-Deselect layer 25, select layer 26
8-Save the updated job file
(And in typical bizarre EAGLE fasion, steps 6/7 only work if you have a board file open because otherwise it does not let you select layers)
Now I have no idea if this is the right solution or not. Running the resulting job output a .pls file in addition to everything else. Can someone experienced with such things verify if this correct? If so, it would be cool to get the default SFE-Special updated to support the solder side silkscreen. Given how tight I pack the component side, its nice to put your name, date and other relevent info on the solder side.
I noticed, too, that the SFE-Special cam file didn’t do the solder side. I also noticed that when you run the SFE-Silkscreenfix.ulp, it places the modified silkscreen on the same layer as your existing silkscreen (woe be to you if you save your board, and then move components around – it leaves little silkscreen-turds which are not attached to any component and have to be manually deleted).
I just found a new silkscreen fix ULP [silk_gen.ulp on the Eagle site which makes two NEW layers (_tsilk and _bsilk) with all of the silk screen information copied to it (and adjusted for minimum line width) so the original layers are unmodified. Then it’s just a matter of updating SFE-Special to use the _tsilk and _bsilk layers.
(woe be to you if you save your board, and then move components around – it leaves little silkscreen-turds which are not attached to any component and have to be manually deleted)
Funny you should mention that as I planned to bring it up once the solder side silkscreen issue was resolved. As I was updating my rev-b, I ran into the double copy items. At first I figured I had somehow gotten careless with copy or smash or something like that. After the 5th or 6th one, I realized it must be from the ULP fixup script. Fortunately I only had a couple of things to update as it messes things up to the point that any significant rework would require the board to be laid out from scratch.
Your idea to use the new ULP and appropriately adjusted SFE-Special CAM job with special layers sounds like a great plan. Did you use that ULP in your submission or was it something you found later? Hopefully we can get this resolved this week as I have more designs to submit (so many plans, so little time) .
I downloaded the silk_gen.ulp file from the Eagle site, but it had a few issues (not the least of which is that it was written in a horrible style). I rewrote large portions of it, added a bit of user-interface to it, and have put it up on my site, along with a fixed version of the CAM to reference the new layers.
When you run silk_gen.ulp, it will pop up a dialog asking you what layers you want to include in the new merged silkscreen layer, as well as the name and layer numbers of the generated layers.
It will then write a script to create two new layers (by default, _tsilk and _bsilk), and draw all of the silk-screening in place on the new layers. It also has an option to delete those layers before re-generating them, that way, if you rev your board, you always have a clean start.
The modified CAM file expects the _tsilk and _bsilk layers to be present, so run the ULP before running the CAM job.
I’m pretty sure that the linked-to silk_gen.ulp could replace the SFE-SilkScreenFix.ulp … and the CAM file linked-to above has the corrections to get the bottom silk-screen.
maybe i’ll make the silk_gen.ulp run the CAM file after it’s done… I wonder if I could make the ULP run an external program (winzip) to zip up the output files, too…
It looks like while the SFE-Special file has been updated, the ULP has not and that appears to be a dangerous combination. For my order I used the files that Pryankster posted as I don’t think the current SFE files are going to work. Looks like the ULP still generates its output to the existing silkscreen layers but that the CAM job looks for the data in layers 121/122 and thus won’t find it.
Pryankster-- two minor suggestions for the ULP:
1- Turn on the soldermask layers when it completes
2- Turn off the source silkscreen layers 21/22/25/26/27/28 so it ends up showing just final silkscreen output.
3- Since Nathan mentioned in a previous thread that having the board outline on the silkscreen was helpful, would it be possible for the ULP to add that as well (presumably just copy layer 20 to 121).
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