I’m using this cam job, and I would like to what in the heck is layer 121 that seem to go into the plc file(s).
Silk screen CMP - write the plc file calling out layer 121 which appears to be some odd drill file. It also gives the error “No layers active”
Silk screen SOL - Outputs layer 122 to pls.
If you look at thease in gc prevue, they seem to some kind of drill file.
What gives?
JimD:
I’m using this cam job, and I would like to what in the heck is layer 121 that seem to go into the plc file(s).Silk screen CMP - write the plc file calling out layer 121 which appears to be some odd drill file. It also gives the error “No layers active”
Silk screen SOL - Outputs layer 122 to pls.
If you look at thease in gc prevue, they seem to some kind of drill file.
Greetings JimD,
The layers 121 and 122 are created from other layers, and used to produce reliable silk screens on your PCB. The reason is simple; EAGLE defaults to narrow line widths that can’t be reproduced on the BatchPCB fab process. Without this step you may loose some or all of your fine line silk screen detail.
The macro “silk_gen.ulp” should be run on your PCB design before the CAM job, to convert all existing silk screen data (layers 21, 25, 27 for top, and layers 22, 26, 28 for bottom).
You may edit the new layers (121 and 122) or edit the other layers before running silk-gen to suit your needs. Be warned that edits on layer 121 and 122 will be lost if you run silk-gen a second time (well, unless you turn off the switch in the dialog box when the macro starts).
Another issue, take care if you change the text ratio in your library parts or board design - it can generate errors later when you run silk_gen.
I’d suggest getting in the habit of inspecting your work in EAGLE with all layers turned off except 121, then again with 122 only. What you see will be the final silk screen legend on the actual PCB.
Comments Welcome!
Ok, thats fine. I guess I can modify the ULP to include the layers I want.
One other question - How is the outline of the board determined?
JimD:
One other question - How is the outline of the board determined?
JimD,
Layer 20 is for outlines (called Dimension). You can draw directly on this layer to mark the board edge, or edit the default Dimension rectangle (set to max size when you start a new layout).
There is some continuing debate over how EAGLE defines the board edges and origin. (Perhaps there is a guard band for scored breaks? - not available in BatchPCB). The CAM job can be edited to change the offsets if necessary.
While this hasn’t been an issue for me (yet) its frustrating to see different dims in BatchPCB’s bot output compared with the EAGLE editor dims.
A better method when creating a board is to use a library part. Just add it the schematic, and then position it accurately in the layout editor. This avoids the risk of bumping it as you work the layout, and when required all boards are exactly the same size and shape.
I made a library (PCB_outline) of popular board layouts that fit the ready-made enclosures that I use. In many cases I’ve added witness marks (layer 48) to these to locate mounting holes; switches (that must line up with the panels); and connectors for daughter cards, etc.
Let me know if you’d like a copy of the library as a guide for your projects.
Comments Welcome!
It was my understand in as well that layer 20 defined the board outline.
This gets put into the plc file (top layer silk screen).
I had the same experience - the bot determined a different board size so that my outline on layer 20 appeared as a silk screen line just inside the bots outline.
As I mentioned, i always end up editing the plc generators as I never want name or value in the silk.
I once submit a design with no plc file at all, and the bot figured it out pretty well.
This batch I sent directly to Golden Phoenix (after drc’ing on batchpcb) so we sill see how they interpret it.
Sure, I’d like your outline lib…
Thanks!
JimD:
Sure, I’d like your outline lib…Thanks!
JimD,
Here’s my [PCB_Outlines.lbr for EAGLE. Let me know if you get stuck.
Comments Welcome!](http://www.stonard.com/SFE/PCB_Outlines.lbr)