I’m doing my 1st PCB design and am using a BNC connector that hangs off the edge of my board. The silkscreen for the entire BNC connector appears to be getting calculated in the BatchPCB size dimensions for my board and affecting my total cost per board.
Naturally, I don’t actually want a silkscreen to appear off the board. What do I need to do in these situations?
Tell us what design software you’re using.
If you’re using Eagle, find and run silk_gen.ulp which has the nice side effect of letting you set a minimum silk width, also something you need to worry about with BatchPCB. But anyway it will copy all your silk onto a couple of new layers. Turn off the original silk layers and you’ll find that the new silk layers are editable…delete and resize whatever you want.
I’m using Eagle. I just decided to change the PCB layout of the part. Anything overhanging the board is now on the document layer instead of tplace layer.
Yes, if more part designers thought ahead, they’d do that from the beginning.
It’s pretty amazing how many designs have that problem. It would be good if the library tutorials talked about this. Specifically, what the various documentation layers are for. It took me a while to figure this out.
I guess it would be more worth the effort for Eagle, specifically, if it allowed you to turn layers on and off for specific parts. Sometimes you would like to see the document layer on some parts and not others, so you’re back to the method of regenerating the silk and editing that layer.
After I run silk_gen.ulp I just go back with my delete tool and delete any silk that is outside of my border. This is the best way I found to avoid having the board house “extend” the board out to include this part.
I made the fatal mistake of not doing this one time on some parts. I had several edge-mounted DB9 connectors. When the boards came I had extra board on those edges of the board with a very nice silkscreen of the connector. Had to break out the straight edge and a sharp knief. Luckily there were just prototype boards and I only needed to do a couple.
:?
I’m using the Silk_Gen.ulp as recommended in Jason of rpcelectronics excellent YouTube tutorials but I think I must be doing something wrong as I get errors related to all my text sizes and the final product looks terrible.
Here’s what my board looks like before I run the .ulp:
Here is an example of the error I get (one for every bit of text, I believe):
Here’s what the board looks like after the .ulp finishes:
What am I doing wrong?
Your text is too small bro. you will not be able to read that once it’s printed. You need to make it at least 0.032 for people to read it.
I’m using a 1mm grid and the text is 0.4064 (I’m assuming that’s also in mm) so I see what you mean (I converted my grid to inches and ‘0.032’ is larger than what it was at 0.4064).
If I first increase the size of the text to a minimum of 0.032 and then run silk_gen.ulp, will it look better or just make the text bigger?
Another quick question: If I deselect the ‘Delete existing silk screen layer’ when starting silk_gen.ulp, will it keep any separate text I’ve added to layer 121?
I have never used silk_gen.ulp and had to look it up. Looks like all it does is it sets the line width of the silkscreen and puts them on separate layers. Not exactly sure why you are using this…?
If you are using 1 mm grid, the size of your characters are tiny. Whatever that ulp is doing to the silkscreen is the reason you have errors. I usually just put my silkscreen on the layer “tplace” like the rest of the libraries do. Then use the size 0.032" or above and also change them to vector fonts. That’s it. I only change the width to above 8% when I use large letters. You can do all this by right clicking the silkscreen you want to change and hitting properties.
Thanks codlink. This is my first Eagle Cadsoft project so it’s all new to me. I’ve been watching Jason’s YouTube tutorials and he mentioned this ulp and it made sense to me as how else do you generate the silkscreen layer? Is that otherwise done during the Gerber file creation process?
It’s generated during the Gerber process. It depends on what PCB fab company you are using as to what files they accept. I use OSH Park or Itead to fab my boards. They need different labels on the Gerber files. OSH Park uses the .ger extension and Itead uses .GTL, .GTO (top silkscreen), .GTS, .GBL, .GBO (Bottom silkscreen), .GBS extensions.
If you haven’t picked out a company yet, I would highly recommend OSH Park. Their boards are top quality at a good price.
If you haven’t looked Sparkfun’s Eagle tutorials, you should check them out.
Schematic Tut:
http://www.sparkfun.com/tutorials/108
PCB Tut:
Thanks again codlink. I have gone over those tutorials and noted that they only add board title text to the silkscreen layer although it’s a bit unclear (one of their checks is, "Silkscreen title and pin labels’ under ‘Things to check on every layout:’ but the tutorial itself says to add this to the tPlace layer)
I changed all the text to be 0.032" but I still get this error:
Here’s the text details:
I may just give up on generating this silk screen layer and follow the SparkFun tutorial instead …
What are you using to get that error? The DRC?
run silk_gen.ulp
DRC/ERC show no errors.
My advice, don’t use it. I never have and my boards come out perfect.
Thanks codlink. So you just add extra text (board name, for example) to tPlace layer and then run see-gerb274x.cam?
I just submitted my Gerber files to BatchPCB (2nd try - got bottom copper spacing errors first time around). Fingers crossed …