RossWaddell:
Thanks codlink. So you just add extra text (board name, for example) to tPlace layer and then run see-gerb274x.cam?
Yep. Do a Google search for a Gerber file viewer. This let’s you see your board outside of Eagle so you can see if anything is messed up.
I just submitted my Gerber files to BatchPCB (2nd try - got bottom copper spacing errors first time around). Fingers crossed …
If you read the forum “Batch PCB,” you will see alot of people are having issues with the new site. OSH Park has the easiest upload system. Just upload the gerber files and it will show you every layer plus layers combined.
I downloaded and installed gerbv 2.60 but I can’t see how to tell if there are problems with my layers. Plus, as you can see below, although my component names are on the tNames layer they didn’t show up in the top silkscreen layer:
(I didn’t use silk_gen.ulp; I just ran the CAM job)
What cam job did you run? When you have the job window open look through the tabs. On the tab for the silkscreen make sure all the layers for your silkscreen are highlighted. i.e. tnames, tplace, etc…
If you still are having problems, attach your .sch and .brd files to a post and I will look at them. But will need to know what job you are running.
I’m using the one from the SparkFun tutorial - sfe-gerb274x.cam. I see that it only has tPlace selected. So that explains it. I re-ran the job with tNames added and it looks good.