I got most of the lines to go away by turning off the cut lines and crop marks, but I’m still getting one. Any ideas?
That's a silk-screen layer image? Either the scale is offLooseTooth:
I got most of the lines to go away by turning off the cut lines and crop marks, but I’m still getting one. Any ideas?
or are all those flea bites supposed to be text?
bigglez:
That's a silk-screen layer image? Either the scale is offLooseTooth:
I got most of the lines to go away by turning off the cut lines and crop marks, but I’m still getting one. Any ideas?or are all those flea bites supposed to be text?
It’s the silkscreen. It’s really just there to enlarge and print out. I decided to uniformly label all of the 402 parts by placing the component name and value in between the pads. Those boards are about 1"x1".
LooseTooth:
It’s the silkscreen. It’s really just there to enlarge and print out. I decided to uniformly label all of the 402 parts by placing the component name and value in between the pads. Those boards are about 1"x1".
What size text are you using? BatchPCB doesn’t do well with
any line stroke smaller than 10mils.
Why add both component designator and value? Most
SMT parts are not human readable, and if your prototypes
are anything like mine you’ll probably tweak values anyway.
If you’re not serious about functional silkscreen on your PCB
panel then why spend time on Gerbemerge for the silk
layers?
Wouldn’t a non-BatchPCB PCB without silkscreen be both
quicker turn and cheaper? BatchPCB will ignore missing
silkscreen layers (and/or you can add a text comment -
no silk - when you upload and order with SFE).
bigglez:
What size text are you using?
size 10
bigglez:
Why add both component designator and value? MostSMT parts are not human readable, and if your prototypes
are anything like mine you’ll probably tweak values anyway.
I have considered using only the values. I think I’d rather keep the names in there also for the purpose of printing out a cheat sheet. I am prototyping a few parts here, such as power supplies for the purpose of miniaturization, but otherwise it is a proven design that we have been using for over a year. I doubt I will change any of the cap/res values.
bigglez:
If you’re not serious about functional silkscreen on your PCBpanel then why spend time on Gerbemerge for the silk
layers?
This point is hard to argue with. I guess for one, I am just trying to complete this whole process, from Eagle to hardware, so that I have that as an ability in the future.
bigglez:
Wouldn’t a non-BatchPCB PCB without silkscreen be bothquicker turn and cheaper? BatchPCB will ignore missing
silkscreen layers (and/or you can add a text comment -
no silk - when you upload and order with SFE).
I have no intention of using Batch-PCB. Whenever I do finally finish a board, I almost always need it ‘right away’.
Well, taking a second look, there is an issue in the top copper layer as well. I’ll probably fiddle with the config file for a few more minutes and then give up. I’ll just not use those two boards. I’ll still have 60 good panels over two boards, and there is a good chance I made at least one mistake anyway, so who cares!
It turned out that it was a bug in gerbview! Thanks for the help I received in PM.
Considering I use Gerbview quite a bit, was this an error that you were able to work around?
brennen:
Considering I use Gerbview quite a bit, was this an error that you were able to work around?
Nope. Editing the ‘merged’ files so that gerbview displays them correctly, is beyond my scope. Sorry 