Dimension Layer 20 Eagle

:smiley: Just got my first Batch Board from Sparkfun very nice the only question is the board was not routed to the outlined dimension as layed out in the Layer 20 on the eagle file. I followed the tutorial on the BatchPCB site but there does not seem to be a file for routing information. BatchPCB supports routed out shape boards but no file type is specified :?:

Pete

pmhunt:
:smiley: Just got my first Batch Board from Sparkfun very nice the only question is the board was not routed to the outlined dimension as layed out in the Layer 20 on the eagle file. I followed the tutorial on the BatchPCB site but there does not seem to be a file for routing information.

Greetings Pete,

Sorry to hear that your board is not exactly as you expected. How far off is it? Did you use the BatchPCB tools (drillcfg.ulp, silk_gen.ulp, and SFE-Special.cam)? Did you check your Gerbers (with a third party viewer) before sending to BatchPCB?

It’s my understanding that the bot extracts the two largest dims in X and Y to define a rectangle for the board outline. Typically, these numbers are in the layer 20 data, which is merged to the *.plc file.

During the ordering process there are two checks (the bot gives you the largest X and Y dims as numbers, and the bot email link has a composite image of the top layer, filled pads, filled vias, top soldermask, and top silk. Did yours look correct before you ordered?

Also, if you want to do something beyond a plain rectangle there is a place to attach a CAD drawing (jpg works) of the board outline and enter a text message to the folks at BatchPCB. This file can be zipped with the CAM output files and manually placed in the right slot during the bot step 1 (“Keep Out Layer”).

Comments Welcome!

I did use the BatchPCB tools (drillcfg.ulp, silk_gen.ulp, and SFE-Special.cam)? then checked the Gerbers with a viewer.

I thought that the outline routing data was going to be in the .drd file thus you would not see it. I have used other Board House and the layer 20 information was include in the silk screen information. Using the silk_gen.ulp the layer 20 is not include in the silk screen.

I was not disappointed with the results that I received from BatchPCB I just wish to improve the next time that I use the service. I want to learn from my mistakes !. Is it worth producing a milling file for the layer 20 information ?

Pete

pmhunt:
I did use the BatchPCB tools (drillcfg.ulp, silk_gen.ulp, and SFE-Special.cam)? then checked the Gerbers with a viewer.

Pete,

Glad to hear that you can use the board that you received.

pmhunt:
I thought that the outline routing data was going to be in the .drd file thus you would not see it. I have used other Board House and the layer 20 information was include in the silk screen information. Using the silk_gen.ulp the layer 20 is not include in the silk screen.

The *.drd, *.dri, and .drl files contain data about holes only. You can open these with a text editor (MS WordPad) and inspect the format.

The layer 20 data is combined with both silk-screen layers (*.plc and *.pls). You can view these with an RS274x compatible viewer.

pmhunt:
I was not disappointed with the results that I received from BatchPCB I just wish to improve the next time that I use the service. I want to learn from my mistakes !. Is it worth producing a milling file for the layer 20 information ?

Me too. I seek to improve with each PCB. I wouldn’t bother with extracting the data or creating a new layer.

I’d suggest going back to the email that BatchPCB sent and check the X and Y dims against the values you read (and expected) in the EAGLE board editor. How far off your expectation was the final board? Was your actual board larger or smaller than expected? Was the board a simple rectangle or did you expect it to include additional routing? (BatchPCB will do fancy routing, as long as there are no internal routing - meaning areas cut out yet completely enclosed by the board outline).

On a related note, I got back two BatchPCB boards on Saturday. They are off a bit in actual outside dimensions, enough to bind when fit inside the enclosure which has extruded slots. I’ll probably post some data in a new thread, see if this is an exception or typical tolerance for BatchPCB. As one fits well (as do earlier boards built on the same EAGLE library) I think it might be an isolated case of poor routing.

Comments Welcome!

I have never understood why batchpcb doesn’t support the outline layer. That is the only way to get exactly what you want. It would certainly make things more precise.

The best bet is to copy the outline onto the silk layer which will then define your routing border when they do the calculations. I never did find out what they actually route to. I’d guess something like 20 mils outside their deduced border.