STM32 SWJ test

Development Boards MicroMod
1

I success to enter into SWJ mode and read the SWJ_ID, but(signal after JTAG_TO_SWJ sequence):

http://www.simonqian.com/image/swj.jpg

Note Trn of STM32 is 0.

Any one know why?

Is there anything I missed?

2

8 more clocks should be driven low(IDLE clocks).

Another problem:

After enter into SWD mode and readout DPIDR, according to ADIv5.1.

In

int ahbap_debugport_init(swjdp_common_t *swjdp)

{

uint32_t idreg, romaddr, dummy;

uint32_t ctrlstat;

int cnt = 0;

int retval;

LOG_DEBUG(" ");

swjdp->apsel = 0;

swjdp->ap_csw_value = -1;

swjdp->ap_tar_value = -1;

swjdp->trans_mode = TRANS_MODE_ATOMIC;

dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); // returns 0x00000000

http://www.SimonQian.com/image/swj1.jpg

dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);

http://www.SimonQian.com/image/swj2.jpg

dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); // returns 0xC0000008

http://www.SimonQian.com/image/swj3.jpg

swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;

dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);

dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); // returns 0x34000000

if ((retval = jtag_execute_queue()) != ERROR_OK)

return retval;

/* Check that we have debug power domains activated */

while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) // pass here

{

LOG_DEBUG(“swjdp: wait CDBGPWRUPACK”);

dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);

if ((retval = jtag_execute_queue()) != ERROR_OK)

return retval;

alive_sleep(10);

}

while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) // CSYSPWRUPACK is never set

{

LOG_DEBUG(“swjdp: wait CSYSPWRUPACK”);

dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);

if ((retval = jtag_execute_queue()) != ERROR_OK)

return retval;

alive_sleep(10);

}

dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); // read as 0x34000000

/* With debug power on we can activate OVERRUN checking */

swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;

dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);

dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); // read as 0x34000080

dap_ap_read_reg_u32(swjdp, 0xFC, &idreg); // SWJ fails here

dap_ap_read_reg_u32(swjdp, 0xF8, &romaddr);

LOG_DEBUG(“AHB-AP ID Register 0x%” PRIx32 “, Debug ROM Address 0x%” PRIx32 “”, idreg, romaddr);

return ERROR_OK;

}

3

In SWJ mode, to clear STIKYERR, STKERRCLR should be written to ABORT.

So in ahbap_debugport_init:

swjdp->apsel = 0;

swjdp->ap_csw_value = -1;

swjdp->ap_tar_value = -1;

swjdp->trans_mode = TRANS_MODE_ATOMIC;

dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);

if (dp_jtag)

{

dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);

}

else if (dp_swj)

{

dap_dp_write_reg(swjdp, STKERRCLR, DP_ABORT);

}

dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); // now return 0x00000000

swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CDBGRSTREQ; // without CDBGRSTREQ, CSYSPWRUPACK will be never set

dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);

dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); // read as 0xF4000000

if ((retval = jtag_execute_queue()) != ERROR_OK)

return retval;

/* Check that we have debug power domains activated */

while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))

{

LOG_DEBUG(“swjdp: wait CDBGPWRUPACK”);

dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);

if ((retval = jtag_execute_queue()) != ERROR_OK)

return retval;

alive_sleep(10);

}

while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) // pass

{

LOG_DEBUG(“swjdp: wait CSYSPWRUPACK”);

dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);

if ((retval = jtag_execute_queue()) != ERROR_OK)

return retval;

alive_sleep(10);

}

dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);

/* With debug power on we can activate OVERRUN checking */

swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;

dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);

http://www.SimonQian.com/image/swj5.jpg

dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); // read as 0xF4000080, WDATAERR? How?

http://www.SimonQian.com/image/swj6.jpg

dap_ap_read_reg_u32(swjdp, 0xFC, &idreg); // SWJ fail

dap_ap_read_reg_u32(swjdp, 0xF8, &romaddr);

if I remove the code to enable CORUNDETECT, 2 dap_ap_read_reg_u32 will not fail, but all return 0. After read ap_reg, READOK will be set, but RDBUFF returns 0.