str912 comstick and RESET

Development Boards MicroMod
1

I am using openOCD 0.1.0 with a telnet session on a str912 comstick. Startup of the openOCD and configuration of the access to the board eems to work well. but when I enter the RESET command (RESET, RESET RUN, RESET HALT), the tap str912.cpu gets missconfigured and I have found no possibility, to reconfigure the tap. The only way to continue with work is to shutdown the openOCD, disconnect the stick (power it down) and restart the complete session.

Is somebody out there, who can help?

the main configuration script (openOCD.cfg):

set _CHIPNAME str91x

set _ENDIAN little

telnet_port 4444

gdb_port 3333

debug_level 3

source [find etc/oOCD-interface.cfg]

source [find etc/oOCD-target.cfg]

the interface configuration cript (etc/oOCD-interface.cfg):

interface ft2232

ft2232_device_desc “STR9-comStick A”

ft2232_layout comstick

the target configuration script (etc/oOCD-target.cfg):

jtag_khz 3000

jtag_nsrst_delay 100

jtag_ntrst_delay 100

reset_config trst_and_srst

if { [info exists FLASHTAPID ] } {

set _FLASHTAPID $FLASHTAPID

} else {

set _FLASHTAPID 0x04570041

}

jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID

if { [info exists CPUTAPID ] } {

set _CPUTAPID $CPUTAPID

} else {

set _CPUTAPID 0x25966041

}

jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID

if { [info exists BSTAPID ] } {

set _BSTAPID $BSTAPID

} else {

set _BSTAPID 0x1457f041

}

jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID

set _TARGETNAME [format “%s.cpu” $_CHIPNAME]

target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e

$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0

flash bank str9x 0x00000000 0x00080000 0 0 0

the following is some output from the telnet session (after uccessful startup):

Open On-Chip Debugger

scan_chain

TapName | Enabled | IdCode Expected IrLen IrCap IrMask Instr

—|--------------------|---------|------------|------------|------|------|------|---------

0 | str91x.flash | Y | 0x04570041 | 0x04570041 | 0x08 | 0x01 | 0x01 | 0xff

1 | str91x.cpu | Y | 0x25966041 | 0x25966041 | 0x04 | 0x01 | 0x0f | 0x0c

2 | str91x.bs | Y | 0x1457f041 | 0x1457f041 | 0x05 | 0x01 | 0x01 | 0x1f

poll

target state: running

halt

target state: halted

target halted in ARM state due to debug-request, current mode: User

cpsr: 0x20000010 pc: 0x00004e44

poll

target state: halted

target halted in ARM state due to debug-request, current mode: User

cpsr: 0x20000010 pc: 0x00004e44

scan_chain

TapName | Enabled | IdCode Expected IrLen IrCap IrMask Instr

—|--------------------|---------|------------|------------|------|------|------|---------

0 | str91x.flash | Y | 0x04570041 | 0x04570041 | 0x08 | 0x01 | 0x01 | 0xff

1 | str91x.cpu | Y | 0x25966041 | 0x25966041 | 0x04 | 0x01 | 0x0f | 0x0c

2 | str91x.bs | Y | 0x1457f041 | 0x1457f041 | 0x05 | 0x01 | 0x01 | 0x1f

reset halt

JTAG tap: str91x.flash tap/device found: 0x04570041 (Manufacturer: 0x020, Part: 0x4570, Version: 0x0)

JTAG Tap/device matched

Tap/Device does not have IDCODE

JTAG tap: str91x.cpu got: 0x00000000 (mfg: 0x000, part: 0x0000, ver: 0x0)

JTAG tap: str91x.cpu expected 1 of 1: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)

trying to validate configured JTAG chain anyway…

Could not validate JTAG scan chain, IR mismatch, scan returned 0x000029. tap=str91x.cpu pos=8 expected 0x1 got 0

Could not validate JTAG chain, continuing anyway…

TAP str91x.cpu:

value captured during scan didn’t pass the requested check:

captured: 0x00 check_value: 0x01 check_mask: 0x0f

in_handler: w/o “in_value”, mismatch in SIR

TAP str91x.cpu:

value captured during scan didn’t pass the requested check:

captured: 0x00 check_value: 0x01 check_mask: 0x0f

in_handler: w/o “in_value”, mismatch in SIR

Runtime error, file “embedded:startup.tcl”, line 176:

examine-fails: -104

in procedure ‘ocd_process_reset’

called at file “embedded:startup.tcl”, line 175

Runtime error, file “command.c”, line 456:

scan_chain

TapName | Enabled | IdCode Expected IrLen IrCap IrMask Instr

—|--------------------|---------|------------|------------|------|------|------|---------

0 | str91x.flash | Y | 0x04570041 | 0x04570041 | 0x08 | 0x01 | 0x01 | 0xff

1 | str91x.cpu | Y | 0x00000000 | 0x25966041 | 0x04 | 0x01 | 0x0f | 0x0c

2 | str91x.bs | Y | 0x1457f041 | 0x1457f041 | 0x05 | 0x01 | 0x01 | 0x1f

telenet output after restart of openOCD without power down of the stick:

Open On-Chip Debugger

scan_chain

TapName | Enabled | IdCode Expected IrLen IrCap IrMask Instr

—|--------------------|---------|------------|------------|------|------|------|---------

0 | str91x.flash | Y | 0x04570041 | 0x04570041 | 0x08 | 0x01 | 0x01 | 0xff

1 | str91x.cpu | Y | 0xffffffff | 0x25966041 | 0x04 | 0x01 | 0x0f | 0x0c

2 | str91x.bs | Y | 0x00000000 | 0x1457f041 | 0x05 | 0x01 | 0x01 | 0x1f

:arrow: :arrow: :arrow:

2

The problem seem to depend on a wrong state or content of the CPU. After clearing the whole flash, the RESET commands seems to work now.

Is there any possibility to get information about the current state of the CPU, so that I can recognize that faulty situation?

3

unsure what is causing the problem, i have attached my script for info.

you could try enabling the debug log - it may help?

# debug options
debug_level 3
#log_output openocd.log

# daemon configuration
telnet_port 4000
gdb_port 2000
tcl_port 6000

# comstick ftdi device
interface ft2232
ft2232_device_desc "STR9-comStick A"
ft2232_layout comstick

jtag_khz 3000
jtag_nsrst_delay 100
jtag_ntrst_delay 100

# use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst

# str9 comstick
jtag newtap str912 flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id 0x04570041
jtag newtap str912 cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x25966041
jtag newtap str912 bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id 0x1457f041
target create str912.cpu arm966e -endian little -chain-position str912.cpu
str912.cpu configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 0x4000 -work-area-backup 0

#flash bank <driver> <base> <size> <chip_width> <bus_width>
flash bank str9x 0x00000000 0x00080000 0 0 0
flash bank str9x 0x00080000 0x00008000 0 0 0

init
reset halt

Cheers

Spen

4

I have the same problem…

scoping around, it looks like it’s a openocd problem,

as doing a reset command via telnet… dos a JTAG and cpu RESET signal,

fine, but never generate’s a JTAG clock… so it has no way of reading the cpu state… etc

So having a look at the source… next few days see if I can find the problem…

Lachlan

5

Try the latest svn head for openocd, as quite a bit has changed since 0.1

6

Im using svn:2651M so… not far away from the very latest…

Lachlan.

7

Hi guys… been away for a few weeks. .

so had not much time to do any thing…

But just before I leaf… I check the logic level with that scope

and some strange thing’s are happing during reset…

So I think some how the power too the FTI chip is being turned off

by openocd as the FTDI chip has power control output. which control’s

all the power to the arm… and also the 2 VCC IO power pint of the FTDI

chip.

I should be back home in few days… to test my idea…

if any one else who has the problem can scope… the jtag. and rset

pin’s to see same out out spec voltage’s and wave form… when the problem presents it self, would help.

lachlan

8

First part of the problem is with the hardware design of the str912 comtick board,

the FT2232 have 5 power pin’s, 2 VCC’s, 1 AVCC, VCCIOA and VCCIOB.

The power to the VCCIOA and VCCIOB is controlled by the FTDI PWREN# pin,

via a FET, and 3.3 volt reg. (this also dos the STR912 cpu too.

While the 2 VCC pin’s and AVCC is connected directly too the USB power from the

host, when the chip is reset it, turn’s of the power too the VCCIOA, and VCCIOB

pin’s. and also the str912 cpu, but keeps the power on the FT2232 2 VCC’s and AVCC pin.

This appears to mess up the FT2232 internal driver’s powered from the

VCCIOA and VCCIOB pin’s, this being the JTAG interface and reset too the str912 chip.

the fault shows up as no clock on the JCLK, and low logic HI voltage’s on the

FT2232 JTAG pin’s. Looking at the FTDI data sheet I see they don’t give any warning’s

about turn off the power to VCCIOA and VCCIOB pine’s while power to VCC and AVCC

is applied, but there eamples circuts never show this way of connection, only

power being applied to the VCCIOA-B at the same time as VCC.

Second part of the problem is with the FTDI driver, for Linux, it always

resets the FTDI chip on the board… on a openEx call too there library,

which of course turns the power off/on to the VCCIO lines and str912 chips.

which if your real lucky may works, but for me most of the time it screw’s up the

internal VCCIOA-B driver’s of the FT2232 chip, and you left with openocd reporting

lot’s of JTAG error’s. Once the internal IO drives are messed up. only way to fix

the problem is to power off the board. and wait a while before power on.

And hope your in luck… and works.

The FTDI lib has a con-fig option which is supposed to disable the reset too the FTDI

chip, when you use the openEx call, but setting this option, had no affect.

It still reset the FTDI chip on openEx call.

The FTDI site is not much help, no source. . etc… so I decide to use the hardware

fix of just shorting the FET power in and out together, and there power is aways

on too the VCCIOA-B pin’s… which will of cores make for quite a start up current spike,

when plunging in the unit… and may cause the USB current limit safety circuit to trip.

But for me, it fixs the problems. With the reset, and now I don’t have to endlessly

unplug and plug in the comstick board. When the FTDI chip lock’s up.

I can post/email picture’s of the mode, to the back of the pcb if any one needs it.

I also have the mode to the Linux ftdi_sio driver in the kernel, so you can access

there serial port to communication too the comstick under Linux /dev/ttyS port.

Lachlan