I am in the process of learning how to design a PCB and have some question about vias. I would be happy if you can guide me about them
Do we have a maximum size limit on vias and is there a performance variation related to via size? For example, assume that you are laying out a board and have to place a via. Given that there is enough space, would you place a via of say, 24 mils or go with a larger value of 35 mils. Would there be any significant performance difference between these two?
For (relatively) high speed signals, e.g a 26 Mhz clock, should one avoid a via and take a much longer route to layout a board or is it okay to throw a via and just switch layers?
Vias should be as small as possible, as they can take up a lot of space. It’s best to make connections as short as possible, it minimises EMC problems.
I am in the process of learning how to design a PCB and have some question about vias. I would be happy if you can guide me about them
Do we have a maximum size limit on vias and is there a performance variation related to via size? For example, assume that you are laying out a board and have to place a via. Given that there is enough space, would you place a via of say, 24 mils or go with a larger value of 35 mils. Would there be any significant performance difference between these two?
It depends on at least a few things but the main player for most “hobby” boards is how much current the via is expected to carry. A 0.020" plated via hole is roughly equivalent in terms of area to a trace 0.062" wide and can actually carry more than 3A through a 0.062" board.
The choice to go with 24 or 35 mils largely depends on the design requirements: What sort of currents and durations/duty cycles are you designing for? What temperature rise is acceptable?
For (relatively) high speed signals, e.g a 26 Mhz clock, should one avoid a via and take a much longer route to layout a board or is it okay to throw a via and just switch layers?
For “high speed” traces you need to be careful of all parameters. Added length adds inductance and distributed capacitance and increases the chances of cross-talk and immunity problems. Each added via adds a change in the impedance of the net. As noted above, a small 0.020" via, mathematically, can look like a 0.062" wide trace. So if if you’ve got an 8-mil track leading to such a via and another 8-mil tack leading away on another layer you can see how the impedance changes. Such impedance changes can encourage reflections and phase errors that round off edges etc. As well, layer changes can result in the a track being a different distance from, say, ground and power planes, affecting impedance there too.
Although 26MHz isn’t that high a frequency it’s good practice to consider signal integrity and return paths (breaks in the return path, for example, can lead to noise-generating ground loops etc…) For 26MHz, with a wavelength of more than 11m (assuming V=c), I’d just drop a via (of course it depends on the actual circuit…) When you get into the hundreds of MHz and are routing, say, DDR SDRAM or something I’d suggest getting impedance analysis tools to ensure signal integrity.
Agree with the previous comments, except that there’s no point in going to really tiny vias unless you need to. Very small holes require exotic (eg laser) drilling), and can have issues with plating.
Thank you for all the responses. They are very helpful. I have especially found Blackfin’s post very informative. As far as I understand, there is no performance penalty for using a larger via (I am omitting space related problems) It may even be better for manufacture purposes and smaller impedance changes. Well I may again be wrong at this.
In my application, the signal going through the via is just control logic hence I don’t expect it to be greater than 30 mA but I don’t know about the temperature rise values. I will look into that.
I will also put Blackfin’s advice on impedance analysis to good use. This PCB that I am working on right now is for interfacing a camera operating at 26.6 Mhz but later on, I will much faster signals. DDR memory interface is one of them. Guess I have to make use of serpentining technique and use the length command to check for trace lengths.
@Blackfin: out of curiosity, have you made designs with ADI’s Blackfin processors? I am planning to combine a blackfin and a fpga (spartan 6) in my final design. At my current level, designing the PCB seems impossible but hopefully I will make progress fast.